TW200803673A - Wiring substrate and manufacturing method thereof, and semiconductor apparatus - Google Patents

Wiring substrate and manufacturing method thereof, and semiconductor apparatus Download PDF

Info

Publication number
TW200803673A
TW200803673A TW096121881A TW96121881A TW200803673A TW 200803673 A TW200803673 A TW 200803673A TW 096121881 A TW096121881 A TW 096121881A TW 96121881 A TW96121881 A TW 96121881A TW 200803673 A TW200803673 A TW 200803673A
Authority
TW
Taiwan
Prior art keywords
wiring
wiring pattern
substrate
layer
insulating layer
Prior art date
Application number
TW096121881A
Other languages
English (en)
Chinese (zh)
Inventor
Shigetsugu Muramatsu
Tsuyoshi Kobayashi
Takashi Kurihara
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Publication of TW200803673A publication Critical patent/TW200803673A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09909—Special local insulating pattern, e.g. as dam around component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
TW096121881A 2006-06-19 2007-06-15 Wiring substrate and manufacturing method thereof, and semiconductor apparatus TW200803673A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006168360 2006-06-19
JP2007032106A JP5259095B2 (ja) 2006-06-19 2007-02-13 半導体装置

Publications (1)

Publication Number Publication Date
TW200803673A true TW200803673A (en) 2008-01-01

Family

ID=38537621

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096121881A TW200803673A (en) 2006-06-19 2007-06-15 Wiring substrate and manufacturing method thereof, and semiconductor apparatus

Country Status (5)

Country Link
US (1) US8115300B2 (https=)
EP (1) EP1871153A3 (https=)
JP (1) JP5259095B2 (https=)
KR (1) KR20070120449A (https=)
TW (1) TW200803673A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI470710B (zh) * 2010-10-25 2015-01-21 松下電器產業股份有限公司 電子零件的接合結構
TWI620482B (zh) * 2014-12-18 2018-04-01 英特爾公司 零失準介層墊結構
TWI692283B (zh) * 2018-06-26 2020-04-21 大陸商宏啟勝精密電子（秦皇島）有限公司 柔性電路板及其製作方法

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US7928582B2 (en) * 2007-03-09 2011-04-19 Micron Technology, Inc. Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces
KR100924559B1 (ko) * 2008-03-07 2009-11-02 주식회사 하이닉스반도체 반도체 패키지의 제조 방법
JP2010135347A (ja) * 2008-10-28 2010-06-17 Kyocer Slc Technologies Corp 配線基板およびその製造方法
JP2010165921A (ja) * 2009-01-16 2010-07-29 Kinko Denshi Kofun Yugenkoshi 半導体プロセス、ならびにそれを適用したシリコン基材およびチップパッケージ構造
JP5113114B2 (ja) * 2009-04-06 2013-01-09 新光電気工業株式会社 配線基板の製造方法及び配線基板
JP2011071417A (ja) * 2009-09-28 2011-04-07 Murata Mfg Co Ltd 配線基板の製造方法
KR20130044050A (ko) * 2011-10-21 2013-05-02 에스케이하이닉스 주식회사 반도체 패키지 및 적층 반도체 패키지
JP5801685B2 (ja) * 2011-10-24 2015-10-28 新光電気工業株式会社 配線基板、発光装置及び配線基板の製造方法
KR20140019173A (ko) * 2012-08-06 2014-02-14 삼성전기주식회사 솔더 코팅볼을 이용한 패키징 방법 및 이에 따라 제조된 패키지
US10506722B2 (en) * 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
KR102268781B1 (ko) 2014-11-12 2021-06-28 삼성전자주식회사 인쇄회로기판 및 이를 포함하는 반도체 패키지
WO2016189577A1 (ja) * 2015-05-22 2016-12-01 富士機械製造株式会社 配線形成方法
MY193261A (en) * 2015-07-01 2022-09-28 Qdos Interconnect Sdn Bhd Integrated circuit package
CN106971994A (zh) * 2017-03-01 2017-07-21 江苏长电科技股份有限公司 一种单层板封装结构及其工艺方法
US11328996B2 (en) 2017-12-30 2022-05-10 Intel Corporation Zero-misalignment two-via structures using photoimageable dielectric film buildup film, and transparent substrate with electroless plating
WO2019133015A1 (en) * 2017-12-30 2019-07-04 Intel Corporation Zero-misalignment two-via structures
KR102843099B1 (ko) * 2019-07-12 2025-08-06 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법
WO2021176498A1 (ja) * 2020-03-02 2021-09-10 株式会社Ｆｕｊｉ 配線形成方法
CN121128323A (zh) * 2023-06-13 2025-12-12 株式会社富士 电路形成方法及电路形成装置
EP4716386A1 (en) * 2024-09-19 2026-03-25 Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO Method for manufacturing three-dimensional electrically conductive structure

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Publication number Priority date Publication date Assignee Title
TWI470710B (zh) * 2010-10-25 2015-01-21 松下電器產業股份有限公司 電子零件的接合結構
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TWI620482B (zh) * 2014-12-18 2018-04-01 英特爾公司 零失準介層墊結構
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US10645813B2 (en) 2014-12-18 2020-05-05 Intel Corporation Zero-misalignment via-pad structures
TWI692283B (zh) * 2018-06-26 2020-04-21 大陸商宏啟勝精密電子（秦皇島）有限公司 柔性電路板及其製作方法

Also Published As

Publication number Publication date
EP1871153A3 (en) 2009-04-08
KR20070120449A (ko) 2007-12-24
US8115300B2 (en) 2012-02-14
JP5259095B2 (ja) 2013-08-07
EP1871153A2 (en) 2007-12-26
US20070290306A1 (en) 2007-12-20
JP2008028361A (ja) 2008-02-07

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