TW200623270A - Gate stacks - Google Patents

Gate stacks

Info

Publication number
TW200623270A
TW200623270A TW094134172A TW94134172A TW200623270A TW 200623270 A TW200623270 A TW 200623270A TW 094134172 A TW094134172 A TW 094134172A TW 94134172 A TW94134172 A TW 94134172A TW 200623270 A TW200623270 A TW 200623270A
Authority
TW
Taiwan
Prior art keywords
gate
gate stack
layer
dielectric layer
substrate
Prior art date
Application number
TW094134172A
Other languages
English (en)
Chinese (zh)
Inventor
Dale W Martin
Steven M Shank
Michael C Triplett
Deborah A Tucker
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200623270A publication Critical patent/TW200623270A/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01354—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
TW094134172A 2004-10-01 2005-09-30 Gate stacks TW200623270A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/711,742 US7157341B2 (en) 2004-10-01 2004-10-01 Gate stacks

Publications (1)

Publication Number Publication Date
TW200623270A true TW200623270A (en) 2006-07-01

Family

ID=36126115

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094134172A TW200623270A (en) 2004-10-01 2005-09-30 Gate stacks

Country Status (6)

Country Link
US (2) US7157341B2 (https=)
EP (1) EP1805798B1 (https=)
JP (1) JP2008515240A (https=)
CN (1) CN101032024B (https=)
TW (1) TW200623270A (https=)
WO (1) WO2006039632A2 (https=)

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JP4946860B2 (ja) * 2005-02-17 2012-06-06 コニカミノルタホールディングス株式会社 ガスバリアフィルム及びその製造方法、並びに該ガスバリアフィルムを用いた、有機ｅｌ素子用樹脂基材、有機ｅｌ素子
US8486487B2 (en) 2005-02-17 2013-07-16 Konica Minolta Holdings, Inc. Gas barrier film, gas barrier film manufacturing method, resin substrate for organic electroluminescent device using the aforesaid gas barrier film, and organic electroluminescent device using the aforementioned gas barrier film
US7271079B2 (en) * 2005-04-06 2007-09-18 International Business Machines Corporation Method of doping a gate electrode of a field effect transistor
KR100633988B1 (ko) * 2005-06-23 2006-10-13 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
JP2009026777A (ja) * 2007-07-17 2009-02-05 Renesas Technology Corp 半導体装置の製造方法
US8173532B2 (en) * 2007-07-30 2012-05-08 International Business Machines Corporation Semiconductor transistors having reduced distances between gate electrode regions
CN101728255B (zh) * 2008-10-21 2011-07-20 中芯国际集成电路制造(北京)有限公司 在晶圆上制造栅极的方法
JP2020035789A (ja) 2018-08-27 2020-03-05 キオクシア株式会社 半導体装置
CN118055613A (zh) * 2022-11-08 2024-05-17 长鑫存储技术有限公司 半导体结构及其形成方法

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JPH04142777A (ja) * 1990-10-03 1992-05-15 Kawasaki Steel Corp ゲート電極又は配線の形成方法
JP3316027B2 (ja) * 1993-03-16 2002-08-19 株式会社半導体エネルギー研究所 絶縁ゲート型電界効果半導体装置の作製方法
JP2536413B2 (ja) * 1993-06-28 1996-09-18 日本電気株式会社 半導体集積回路装置の製造方法
US5459091A (en) * 1993-10-12 1995-10-17 Goldstar Electron Co., Ltd. Method for fabricating a non-volatile memory device
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US5545581A (en) * 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
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JP3145929B2 (ja) * 1996-08-15 2001-03-12 日本電気株式会社 半導体装置の製造方法
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FR2765394B1 (fr) 1997-06-25 1999-09-24 France Telecom Procede d'obtention d'un transistor a grille en silicium-germanium
JPH11135773A (ja) * 1997-10-27 1999-05-21 Fujitsu Ltd 半導体装置及びその製造方法
US6278165B1 (en) * 1998-06-29 2001-08-21 Kabushiki Kaisha Toshiba MIS transistor having a large driving current and method for producing the same
US6143611A (en) * 1998-07-30 2000-11-07 Micron Technology, Inc. Semiconductor processing methods, methods of forming electronic components, and transistors
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JP2000269490A (ja) * 1999-03-16 2000-09-29 Fujitsu Ltd 半導体装置の製造方法
US6265297B1 (en) * 1999-09-01 2001-07-24 Micron Technology, Inc. Ammonia passivation of metal gate electrodes to inhibit oxidation of metal
JP2001326348A (ja) * 2000-05-16 2001-11-22 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
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US20020072210A1 (en) * 2000-11-29 2002-06-13 Chi-Min Hsu Method for forming liner layer in sin spacer
JP4932087B2 (ja) * 2001-01-29 2012-05-16 三菱電機株式会社 半導体装置およびその製造方法
US6525953B1 (en) 2001-08-13 2003-02-25 Matrix Semiconductor, Inc. Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
US6812515B2 (en) * 2001-11-26 2004-11-02 Hynix Semiconductor, Inc. Polysilicon layers structure and method of forming same
JP3873771B2 (ja) * 2002-02-22 2007-01-24 ソニー株式会社 半導体装置の製造方法
US7098098B2 (en) 2002-04-16 2006-08-29 Texas Instruments Incorporated Methods for transistors formation using selective gate implantation
JP3487844B1 (ja) * 2002-06-14 2004-01-19 沖電気工業株式会社 Ｌｄｍｏｓ型半導体装置の製造方法
US20040033677A1 (en) * 2002-08-14 2004-02-19 Reza Arghavani Method and apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
US6686637B1 (en) * 2002-11-21 2004-02-03 International Business Machines Corporation Gate structure with independently tailored vertical doping profile
US20050048732A1 (en) * 2003-08-26 2005-03-03 International Business Machines Corporation Method to produce transistor having reduced gate height
US6930362B1 (en) * 2003-10-30 2005-08-16 Lsi Logic Corporation Calcium doped polysilicon gate electrodes

Also Published As

Publication number Publication date
WO2006039632A3 (en) 2006-08-10
WO2006039632A2 (en) 2006-04-13
CN101032024A (zh) 2007-09-05
JP2008515240A (ja) 2008-05-08
US20060073688A1 (en) 2006-04-06
US7378712B2 (en) 2008-05-27
EP1805798A2 (en) 2007-07-11
CN101032024B (zh) 2011-02-09
US7157341B2 (en) 2007-01-02
US20070194385A1 (en) 2007-08-23
EP1805798A4 (en) 2009-08-05
EP1805798B1 (en) 2014-08-13

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