SG85714A1 - Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (cmp) planarization - Google Patents
Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (cmp) planarizationInfo
- Publication number
- SG85714A1 SG85714A1 SG200003913A SG200003913A SG85714A1 SG 85714 A1 SG85714 A1 SG 85714A1 SG 200003913 A SG200003913 A SG 200003913A SG 200003913 A SG200003913 A SG 200003913A SG 85714 A1 SG85714 A1 SG 85714A1
- Authority
- SG
- Singapore
- Prior art keywords
- planarization
- cmp
- fabricating
- gate dielectric
- mechanical polishing
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/359,290 US6200834B1 (en) | 1999-07-22 | 1999-07-22 | Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP) planarization |
Publications (1)
Publication Number | Publication Date |
---|---|
SG85714A1 true SG85714A1 (en) | 2002-01-15 |
Family
ID=23413185
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200003913A SG85714A1 (en) | 1999-07-22 | 2000-07-13 | Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (cmp) planarization |
Country Status (6)
Country | Link |
---|---|
US (1) | US6200834B1 (ja) |
JP (1) | JP2001077321A (ja) |
KR (1) | KR20010015288A (ja) |
CN (1) | CN1150609C (ja) |
SG (1) | SG85714A1 (ja) |
TW (1) | TW440938B (ja) |
Families Citing this family (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6333220B1 (en) * | 1999-06-04 | 2001-12-25 | International Business Machines Corporation | Method and apparatus for providing low-GIDL dual workfunction gate doping with borderless diffusion contact |
US6093661A (en) * | 1999-08-30 | 2000-07-25 | Micron Technology, Inc. | Integrated circuitry and semiconductor processing method of forming field effect transistors |
JP2001127270A (ja) * | 1999-10-27 | 2001-05-11 | Nec Corp | 半導体装置及びその製造方法 |
US6344416B1 (en) * | 2000-03-10 | 2002-02-05 | International Business Machines Corporation | Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions |
US6326260B1 (en) * | 2000-06-22 | 2001-12-04 | International Business Machines Corporation | Gate prespacers for high density, high performance DRAMs |
US6417037B1 (en) * | 2000-07-18 | 2002-07-09 | Chartered Semiconductor Manufacturing Ltd. | Method of dual gate process |
US6346445B1 (en) * | 2000-11-17 | 2002-02-12 | United Microelectronics Corp. | Method for fabricating semiconductor devices with dual gate oxides |
US6468838B2 (en) * | 2001-03-01 | 2002-10-22 | United Microelectronic Corp. | Method for fabricating a MOS transistor of an embedded memory |
KR100364122B1 (en) * | 2001-04-24 | 2002-12-11 | Hynix Semiconductor Inc | Method for fabricating semiconductor device |
US6949479B2 (en) | 2001-06-13 | 2005-09-27 | Micron Technology, Inc. | Methods of forming transistor devices |
KR100650699B1 (ko) * | 2001-06-21 | 2006-11-27 | 삼성전자주식회사 | 별개의 게이트 구조를 갖는 반도체 장치의 게이트 형성방법 |
KR100397176B1 (ko) * | 2001-07-26 | 2003-09-06 | 삼성전자주식회사 | 불휘발성 메모리 장치의 평탄화 방법 |
US6551883B1 (en) * | 2001-12-27 | 2003-04-22 | Silicon Integrated Systems Corp. | MOS device with dual gate insulators and method of forming the same |
US20030109130A1 (en) * | 2001-12-07 | 2003-06-12 | International Business Machines Corporation | Dual-gate process with CMP |
DE10207122B4 (de) * | 2002-02-20 | 2007-07-05 | Advanced Micro Devices, Inc., Sunnyvale | Ein Verfahren zur Herstellung von Schichten aus Oxid auf einer Oberfläche eines Substrats |
US6709926B2 (en) * | 2002-05-31 | 2004-03-23 | International Business Machines Corporation | High performance logic and high density embedded dram with borderless contact and antispacer |
BE1015723A4 (nl) * | 2003-10-17 | 2005-07-05 | Imec Inter Uni Micro Electr | Werkwijze voor het vervaardigen van halfgeleiderinrichtingen met gesilicideerde elektroden. |
US7160771B2 (en) * | 2003-11-28 | 2007-01-09 | International Business Machines Corporation | Forming gate oxides having multiple thicknesses |
US7012021B2 (en) * | 2004-01-29 | 2006-03-14 | Taiwan Semiconductor Mfg | Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device |
US7030012B2 (en) * | 2004-03-10 | 2006-04-18 | International Business Machines Corporation | Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM |
JP4322150B2 (ja) * | 2004-03-15 | 2009-08-26 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7144784B2 (en) * | 2004-07-29 | 2006-12-05 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device and structure thereof |
US20080185667A1 (en) * | 2004-09-17 | 2008-08-07 | Kenichi Yoshino | Thin Film Semiconductor Device and Method for Manufacturing the Same |
KR100697290B1 (ko) * | 2005-09-08 | 2007-03-20 | 삼성전자주식회사 | 이미지 센서의 형성 방법 |
US20080150011A1 (en) * | 2006-12-21 | 2008-06-26 | Spansion Llc | Integrated circuit system with memory system |
US20080203485A1 (en) * | 2007-02-28 | 2008-08-28 | International Business Machines Corporation | Strained metal gate structure for cmos devices with improved channel mobility and methods of forming the same |
CN102543705B (zh) * | 2011-07-12 | 2014-05-28 | 上海华力微电子有限公司 | 用于高、低压器件的多晶硅栅电极集成工艺 |
CN102543706B (zh) * | 2011-07-22 | 2014-06-04 | 上海华力微电子有限公司 | 一种不同多晶硅栅电极厚度的集成工艺 |
CN104952734B (zh) * | 2015-07-16 | 2020-01-24 | 矽力杰半导体技术(杭州)有限公司 | 半导体结构及其制造方法 |
CN111916465A (zh) * | 2019-05-08 | 2020-11-10 | 格科微电子(上海)有限公司 | 提高多栅晶体管中厚栅介质层性能的方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5668035A (en) * | 1996-06-10 | 1997-09-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for fabricating a dual-gate dielectric module for memory with embedded logic technology |
US6015730A (en) * | 1998-03-05 | 2000-01-18 | Taiwan Semiconductor Manufacturing Company | Integration of SAC and salicide processes by combining hard mask and poly definition |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0136935B1 (ko) * | 1994-04-21 | 1998-04-24 | 문정환 | 메모리 소자의 제조방법 |
JPH08130250A (ja) * | 1994-09-05 | 1996-05-21 | Fuji Electric Co Ltd | Mos型集積回路装置の製造方法 |
JPH10163337A (ja) * | 1996-11-28 | 1998-06-19 | Nec Corp | 半導体装置の製造方法 |
KR19980048849A (ko) * | 1996-12-18 | 1998-09-15 | 김광호 | 반도체소자 제조방법 |
JPH11135745A (ja) * | 1997-10-29 | 1999-05-21 | Toshiba Corp | 半導体装置及びその製造方法 |
US6037222A (en) * | 1998-05-22 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company | Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology |
-
1999
- 1999-07-22 US US09/359,290 patent/US6200834B1/en not_active Expired - Fee Related
-
2000
- 2000-03-30 TW TW089105984A patent/TW440938B/zh not_active IP Right Cessation
- 2000-07-12 KR KR1020000039760A patent/KR20010015288A/ko active Search and Examination
- 2000-07-13 SG SG200003913A patent/SG85714A1/en unknown
- 2000-07-20 CN CNB001201905A patent/CN1150609C/zh not_active Expired - Fee Related
- 2000-07-21 JP JP2000220495A patent/JP2001077321A/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5668035A (en) * | 1996-06-10 | 1997-09-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for fabricating a dual-gate dielectric module for memory with embedded logic technology |
US6015730A (en) * | 1998-03-05 | 2000-01-18 | Taiwan Semiconductor Manufacturing Company | Integration of SAC and salicide processes by combining hard mask and poly definition |
Also Published As
Publication number | Publication date |
---|---|
CN1150609C (zh) | 2004-05-19 |
TW440938B (en) | 2001-06-16 |
CN1282103A (zh) | 2001-01-31 |
US6200834B1 (en) | 2001-03-13 |
KR20010015288A (ko) | 2001-02-26 |
JP2001077321A (ja) | 2001-03-23 |
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