SG188723A1 - Etch process for 3d flash structures - Google Patents

Etch process for 3d flash structures Download PDF

Info

Publication number
SG188723A1
SG188723A1 SG2012062352A SG2012062352A SG188723A1 SG 188723 A1 SG188723 A1 SG 188723A1 SG 2012062352 A SG2012062352 A SG 2012062352A SG 2012062352 A SG2012062352 A SG 2012062352A SG 188723 A1 SG188723 A1 SG 188723A1
Authority
SG
Singapore
Prior art keywords
etch
bilayers
recited
pressure
wafer
Prior art date
Application number
SG2012062352A
Other languages
English (en)
Inventor
Le Gouil Anne
R Lindain Jeffrey
Ishikawa Yasushi
Yamaguchi-Adams Yoko
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of SG188723A1 publication Critical patent/SG188723A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
    • H01J37/32816—Pressure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/246—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
SG2012062352A 2011-09-06 2012-08-21 Etch process for 3d flash structures SG188723A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/226,087 US8598040B2 (en) 2011-09-06 2011-09-06 ETCH process for 3D flash structures

Publications (1)

Publication Number Publication Date
SG188723A1 true SG188723A1 (en) 2013-04-30

Family

ID=47753488

Family Applications (1)

Application Number Title Priority Date Filing Date
SG2012062352A SG188723A1 (en) 2011-09-06 2012-08-21 Etch process for 3d flash structures

Country Status (6)

Country Link
US (1) US8598040B2 (cg-RX-API-DMAC10.html)
JP (1) JP6219558B2 (cg-RX-API-DMAC10.html)
KR (1) KR101979957B1 (cg-RX-API-DMAC10.html)
CN (1) CN102983052B (cg-RX-API-DMAC10.html)
SG (1) SG188723A1 (cg-RX-API-DMAC10.html)
TW (1) TWI559393B (cg-RX-API-DMAC10.html)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9384992B2 (en) * 2012-02-09 2016-07-05 Tokyo Electron Limited Plasma processing method
US9299574B2 (en) * 2013-01-25 2016-03-29 Applied Materials, Inc. Silicon dioxide-polysilicon multi-layered stack etching with plasma etch chamber employing non-corrosive etchants
US9129911B2 (en) 2013-01-31 2015-09-08 Applied Materials, Inc. Boron-doped carbon-based hardmask etch processing
US20140342570A1 (en) * 2013-05-16 2014-11-20 Applied Materials, Inc. Etch process having adaptive control with etch depth of pressure and power
JP6211947B2 (ja) 2013-07-31 2017-10-11 東京エレクトロン株式会社 半導体装置の製造方法
JP6140575B2 (ja) * 2013-08-26 2017-05-31 東京エレクトロン株式会社 半導体装置の製造方法
US9018103B2 (en) * 2013-09-26 2015-04-28 Lam Research Corporation High aspect ratio etch with combination mask
JP6267953B2 (ja) 2013-12-19 2018-01-24 東京エレクトロン株式会社 半導体装置の製造方法
CN104793289B (zh) * 2014-01-21 2019-05-10 吉林师范大学 有机聚合物等离子刻蚀工艺误差对器件影响的补偿方法
JP6277004B2 (ja) 2014-01-31 2018-02-07 株式会社日立ハイテクノロジーズ ドライエッチング方法
JP6230930B2 (ja) * 2014-02-17 2017-11-15 東京エレクトロン株式会社 半導体装置の製造方法
JP6289996B2 (ja) 2014-05-14 2018-03-07 東京エレクトロン株式会社 被エッチング層をエッチングする方法
CN105336570A (zh) * 2014-07-14 2016-02-17 北京北方微电子基地设备工艺研究中心有限责任公司 基片刻蚀方法
US20160020119A1 (en) * 2014-07-16 2016-01-21 Macronix International Co., Ltd. Method of Controlling Recess Depth and Bottom ECD in Over-Etching
US9449821B2 (en) * 2014-07-17 2016-09-20 Macronix International Co., Ltd. Composite hard mask etching profile for preventing pattern collapse in high-aspect-ratio trenches
JP6454492B2 (ja) * 2014-08-08 2019-01-16 東京エレクトロン株式会社 多層膜をエッチングする方法
JP6423643B2 (ja) * 2014-08-08 2018-11-14 東京エレクトロン株式会社 多層膜をエッチングする方法
CN105374737B (zh) * 2014-08-25 2019-02-26 中微半导体设备(上海)有限公司 抑制刻蚀过程中孔底部出现缺口的方法、孔的形成方法
JP6328524B2 (ja) * 2014-08-29 2018-05-23 東京エレクトロン株式会社 エッチング方法
JP6339961B2 (ja) 2015-03-31 2018-06-06 東京エレクトロン株式会社 エッチング方法
JP6339963B2 (ja) 2015-04-06 2018-06-06 東京エレクトロン株式会社 エッチング方法
JP6498022B2 (ja) * 2015-04-22 2019-04-10 東京エレクトロン株式会社 エッチング処理方法
US9613824B2 (en) 2015-05-14 2017-04-04 Tokyo Electron Limited Etching method
JP6541439B2 (ja) * 2015-05-29 2019-07-10 東京エレクトロン株式会社 エッチング方法
JP6494424B2 (ja) * 2015-05-29 2019-04-03 東京エレクトロン株式会社 エッチング方法
KR20170002764A (ko) 2015-06-29 2017-01-09 삼성전자주식회사 반도체 소자의 제조 방법
US9613979B2 (en) 2015-07-16 2017-04-04 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same
JP6557588B2 (ja) * 2015-12-04 2019-08-07 株式会社日立ハイテクノロジーズ ドライエッチング方法
US9997374B2 (en) * 2015-12-18 2018-06-12 Tokyo Electron Limited Etching method
GB201608926D0 (en) * 2016-05-20 2016-07-06 Spts Technologies Ltd Method for plasma etching a workpiece
JP6604911B2 (ja) * 2016-06-23 2019-11-13 東京エレクトロン株式会社 エッチング処理方法
US9997366B2 (en) * 2016-10-19 2018-06-12 Lam Research Corporation Silicon oxide silicon nitride stack ion-assisted etch
JP6945388B2 (ja) 2017-08-23 2021-10-06 東京エレクトロン株式会社 エッチング方法及びエッチング処理装置
JP6883495B2 (ja) 2017-09-04 2021-06-09 東京エレクトロン株式会社 エッチング方法
US10002746B1 (en) * 2017-09-13 2018-06-19 Lam Research Corporation Multi regime plasma wafer processing to increase directionality of ions
US10847374B2 (en) * 2017-10-31 2020-11-24 Lam Research Corporation Method for etching features in a stack
JP2019096666A (ja) * 2017-11-20 2019-06-20 東京エレクトロン株式会社 エッチング方法及びこれを用いた窪みパターンの埋め込み方法
KR102762670B1 (ko) * 2017-11-30 2025-02-04 램 리써치 코포레이션 실리콘 옥사이드 실리콘 나이트라이드 스택 계단 단차 (stair step) 에칭
TWI819233B (zh) * 2019-08-15 2023-10-21 美商應用材料股份有限公司 非共形膜的選擇性蝕刻臨界尺寸控制
JP7403314B2 (ja) * 2019-12-26 2023-12-22 東京エレクトロン株式会社 エッチング方法及びエッチング装置
CN111154490A (zh) * 2020-01-02 2020-05-15 长江存储科技有限责任公司 刻蚀气体、刻蚀方法及3d存储器件制造方法
CN115380365A (zh) 2020-02-13 2022-11-22 朗姆研究公司 具有无穷大选择性的高深宽比蚀刻
WO2021168134A1 (en) 2020-02-19 2021-08-26 Lam Research Corporation Graphene integration
US11688609B2 (en) * 2020-05-29 2023-06-27 Tokyo Electron Limited Etching method and plasma processing apparatus
JP7641923B2 (ja) 2022-01-27 2025-03-07 東京エレクトロン株式会社 エッチング方法及びプラズマ処理装置
JP7675033B2 (ja) 2022-01-27 2025-05-12 東京エレクトロン株式会社 エッチング方法及びプラズマ処理装置

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62232925A (ja) * 1986-04-03 1987-10-13 Sony Corp Ｓｉのエツチングガス
US5827437A (en) * 1996-05-17 1998-10-27 Lam Research Corporation Multi-step metallization etch
US6127278A (en) * 1997-06-02 2000-10-03 Applied Materials, Inc. Etch process for forming high aspect ratio trenched in silicon
EP1019958B1 (de) * 1997-09-24 2003-04-23 Infineon Technologies AG Verfahren zur ausbildung einer grabenstruktur in einem siliziumsubstrat
US6312616B1 (en) * 1998-12-03 2001-11-06 Applied Materials, Inc. Plasma etching of polysilicon using fluorinated gas mixtures
US6303513B1 (en) * 1999-06-07 2001-10-16 Applied Materials, Inc. Method for controlling a profile of a structure formed on a substrate
JP4343379B2 (ja) * 2000-02-24 2009-10-14 キヤノンマーケティングジャパン株式会社 基板処理方法および基板処理装置ならびにデバイス製造方法
JP4653395B2 (ja) * 2000-09-29 2011-03-16 株式会社日立製作所 プラズマ処理装置
SG152920A1 (en) * 2002-10-11 2009-06-29 Lam Res Corp A method for plasma etching performance enhancement
US6969568B2 (en) * 2004-01-28 2005-11-29 Freescale Semiconductor, Inc. Method for etching a quartz layer in a photoresistless semiconductor mask
US7090782B1 (en) * 2004-09-03 2006-08-15 Lam Research Corporation Etch with uniformity control
US7459100B2 (en) * 2004-12-22 2008-12-02 Lam Research Corporation Methods and apparatus for sequentially alternating among plasma processes in order to optimize a substrate
JP4663368B2 (ja) * 2005-03-28 2011-04-06 東京エレクトロン株式会社 プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
JP4768557B2 (ja) * 2006-09-15 2011-09-07 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP4450245B2 (ja) * 2007-06-07 2010-04-14 株式会社デンソー 半導体装置の製造方法
CN101339903A (zh) * 2007-06-27 2009-01-07 应用材料股份有限公司 用于高温蚀刻高-k材料栅结构的方法
JP5376789B2 (ja) * 2007-10-03 2013-12-25 株式会社東芝 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の制御方法
CN103258729B (zh) * 2007-12-21 2016-07-06 朗姆研究公司 硅结构的制造和带有形貌控制的深硅蚀刻
US20090191711A1 (en) * 2008-01-30 2009-07-30 Ying Rui Hardmask open process with enhanced cd space shrink and reduction
JP2011124239A (ja) * 2008-03-31 2011-06-23 Daikin Industries Ltd ドライエッチングガス及びそれを用いたドライエッチング方法
JP2009277770A (ja) * 2008-05-13 2009-11-26 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US8394722B2 (en) * 2008-11-03 2013-03-12 Lam Research Corporation Bi-layer, tri-layer mask CD control
JP2010177652A (ja) * 2009-02-02 2010-08-12 Toshiba Corp 半導体装置の製造方法
JP2010272758A (ja) * 2009-05-22 2010-12-02 Hitachi High-Technologies Corp 被エッチング材のプラズマエッチング方法
DE102010038736A1 (de) * 2010-07-30 2012-02-02 Globalfoundries Dresden Module One Llc & Co. Kg Verfahren zum Steuern der kritischen Abmessungen von Gräben in einem Metallisierungssystem eines Halbleiterbauelements während des Ätzens einer Ätzstoppschicht

Also Published As

Publication number Publication date
TW201330088A (zh) 2013-07-16
JP6219558B2 (ja) 2017-10-25
KR20130026996A (ko) 2013-03-14
CN102983052A (zh) 2013-03-20
US20130059450A1 (en) 2013-03-07
JP2013080909A (ja) 2013-05-02
KR101979957B1 (ko) 2019-05-17
US8598040B2 (en) 2013-12-03
TWI559393B (zh) 2016-11-21
CN102983052B (zh) 2015-09-02

Similar Documents

Publication Publication Date Title
US8598040B2 (en) ETCH process for 3D flash structures
US10002773B2 (en) Method for selectively etching silicon oxide with respect to an organic mask
US11646207B2 (en) Silicon oxide silicon nitride stack stair step etch
US20140051256A1 (en) Etch with mixed mode pulsing
US8609548B2 (en) Method for providing high etch rate
SG189609A1 (en) Etch with pulsed bias
US20260076118A1 (en) Method for etching features in a stack
US10600648B2 (en) Silicon-based deposition for semiconductor processing
SG193076A1 (en) Controlled gas mixing for smooth sidewall rapid alternating etch process
WO2024059467A1 (en) Method for etching features using hf gas
US10546756B2 (en) Method for generating vertical profiles in organic layer etches
US9607848B2 (en) Etch process with pre-etch transient conditioning
US9997364B2 (en) High aspect ratio etch
US8906248B2 (en) Silicon on insulator etch
WO2019168535A1 (en) Silicon-based deposition for semiconductor processing
WO2024178234A1 (en) Method for etching features in a stack