SG168461A1 - Method for fabricating a semiconductor substrate - Google Patents
Method for fabricating a semiconductor substrateInfo
- Publication number
- SG168461A1 SG168461A1 SG201003856-0A SG2010038560A SG168461A1 SG 168461 A1 SG168461 A1 SG 168461A1 SG 2010038560 A SG2010038560 A SG 2010038560A SG 168461 A1 SG168461 A1 SG 168461A1
- Authority
- SG
- Singapore
- Prior art keywords
- impurity
- substrate
- semiconductor substrate
- semiconductor
- fabricating
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title abstract 7
- 239000004065 semiconductor Substances 0.000 title abstract 6
- 238000000034 method Methods 0.000 title abstract 2
- 239000012535 impurity Substances 0.000 abstract 9
- 239000002019 doping agent Substances 0.000 abstract 2
- 238000011109 contamination Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Recrystallisation Techniques (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP09290609A EP2282332B1 (en) | 2009-08-04 | 2009-08-04 | Method for fabricating a semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG168461A1 true SG168461A1 (en) | 2011-02-28 |
Family
ID=41503765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG201003856-0A SG168461A1 (en) | 2009-08-04 | 2010-06-02 | Method for fabricating a semiconductor substrate |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8058149B2 (ko) |
| EP (1) | EP2282332B1 (ko) |
| JP (1) | JP5666842B2 (ko) |
| KR (1) | KR101698434B1 (ko) |
| CN (1) | CN101989567B (ko) |
| SG (1) | SG168461A1 (ko) |
| TW (1) | TWI492274B (ko) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2977069B1 (fr) | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
| JPWO2013031868A1 (ja) * | 2011-08-30 | 2015-03-23 | 有限会社Ｍｔｅｃ | 化合物半導体装置及びその製造方法 |
| CN106489187B (zh) * | 2014-07-10 | 2019-10-25 | 株式会社希克斯 | 半导体基板和半导体基板的制造方法 |
| FR3057396B1 (fr) * | 2016-10-10 | 2018-12-14 | Soitec | Substrat pour capteur d'image de type face avant et procede de fabrication d'un tel substrat |
Family Cites Families (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5137837A (en) | 1990-08-20 | 1992-08-11 | Hughes Aircraft Company | Radiation-hard, high-voltage semiconductive device structure fabricated on SOI substrate |
| JP3211998B2 (ja) * | 1993-05-31 | 2001-09-25 | ソニー株式会社 | 半導体装置製造方法 |
| JP3542376B2 (ja) * | 1994-04-08 | 2004-07-14 | キヤノン株式会社 | 半導体基板の製造方法 |
| US6107213A (en) | 1996-02-01 | 2000-08-22 | Sony Corporation | Method for making thin film semiconductor |
| US6326280B1 (en) | 1995-02-02 | 2001-12-04 | Sony Corporation | Thin film semiconductor and method for making thin film semiconductor |
| JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
| JP2002110688A (ja) * | 2000-09-29 | 2002-04-12 | Canon Inc | Ｓｏｉの熱処理方法及び製造方法 |
| JP2002134722A (ja) * | 2000-10-26 | 2002-05-10 | Sumitomo Metal Ind Ltd | Ｓｏｉウェーハの製造方法及びｓｏｉウェーハ |
| EP1570528B1 (en) | 2002-12-09 | 2019-05-29 | Quantum Semiconductor, LLC | Cmos image sensor |
| US20070069335A1 (en) * | 2003-09-08 | 2007-03-29 | Akihiko Endo | Bonded wafer and its manufacturing method |
| JP2006108365A (ja) * | 2004-10-05 | 2006-04-20 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| US7238583B2 (en) * | 2005-02-11 | 2007-07-03 | Sarnoff Corporation | Back-illuminated imaging device and method of fabricating same |
| JP2007059873A (ja) * | 2005-07-26 | 2007-03-08 | Sharp Corp | 半導体発光素子及びその製造方法 |
| US7446018B2 (en) * | 2005-08-22 | 2008-11-04 | Icemos Technology Corporation | Bonded-wafer superjunction semiconductor device |
| JP2007059704A (ja) * | 2005-08-25 | 2007-03-08 | Sumco Corp | 貼合せ基板の製造方法及び貼合せ基板 |
| US7745309B2 (en) * | 2006-08-09 | 2010-06-29 | Applied Materials, Inc. | Methods for surface activation by plasma immersion ion implantation process utilized in silicon-on-insulator structure |
| WO2008029607A1 (en) * | 2006-09-07 | 2008-03-13 | Nec Electronics Corporation | Manufacturing method of semiconductor substrate and manufacturing method of semiconductor device |
| CN101281912B (zh) * | 2007-04-03 | 2013-01-23 | 株式会社半导体能源研究所 | Soi衬底及其制造方法以及半导体装置 |
| JP5220335B2 (ja) * | 2007-04-11 | 2013-06-26 | 信越化学工業株式会社 | Ｓｏｉ基板の製造方法 |
| CN101669193B (zh) * | 2007-04-27 | 2012-02-15 | 株式会社半导体能源研究所 | Soi衬底及其制造方法和半导体器件 |
| JP5272329B2 (ja) * | 2007-05-22 | 2013-08-28 | 信越半導体株式会社 | Ｓｏｉウエーハの製造方法 |
| KR100873299B1 (ko) | 2007-08-20 | 2008-12-11 | 주식회사 실트론 | Ｓｓｏｉ 기판의 제조방법 |
| US8101501B2 (en) * | 2007-10-10 | 2012-01-24 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor device |
| US8093136B2 (en) * | 2007-12-28 | 2012-01-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| EP2105957A3 (en) * | 2008-03-26 | 2011-01-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate and method for manufacturing semiconductor device |
| DE112009000788T5 (de) * | 2008-04-25 | 2011-04-21 | ULVAC, Inc., Chigasaki-shi | Herstellungsverfahren für Solarzellen, Herstellungsvorrichtung für Solarzellen sowie Solarzelle |
| JP2010114409A (ja) * | 2008-10-10 | 2010-05-20 | Sony Corp | Ｓｏｉ基板とその製造方法、固体撮像装置とその製造方法、および撮像装置 |
| US7955940B2 (en) * | 2009-09-01 | 2011-06-07 | International Business Machines Corporation | Silicon-on-insulator substrate with built-in substrate junction |
-
2009
- 2009-08-04 EP EP09290609A patent/EP2282332B1/en active Active
-
2010
- 2010-05-28 KR KR1020100050087A patent/KR101698434B1/ko active IP Right Grant
- 2010-06-02 SG SG201003856-0A patent/SG168461A1/en unknown
- 2010-06-03 TW TW099118002A patent/TWI492274B/zh active
- 2010-06-14 US US12/815,262 patent/US8058149B2/en active Active
- 2010-06-18 CN CN201010223760.0A patent/CN101989567B/zh active Active
- 2010-07-15 JP JP2010160843A patent/JP5666842B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20110034006A1 (en) | 2011-02-10 |
| CN101989567A (zh) | 2011-03-23 |
| KR20110014083A (ko) | 2011-02-10 |
| EP2282332A1 (en) | 2011-02-09 |
| TWI492274B (zh) | 2015-07-11 |
| EP2282332B1 (en) | 2012-06-27 |
| JP2011035390A (ja) | 2011-02-17 |
| JP5666842B2 (ja) | 2015-02-12 |
| US8058149B2 (en) | 2011-11-15 |
| KR101698434B1 (ko) | 2017-01-20 |
| CN101989567B (zh) | 2015-03-04 |
| TW201110199A (en) | 2011-03-16 |
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