SG134208A1 - A method of fabricating a composite substrate - Google Patents

A method of fabricating a composite substrate

Info

Publication number
SG134208A1
SG134208A1 SG200608374-5A SG2006083745A SG134208A1 SG 134208 A1 SG134208 A1 SG 134208A1 SG 2006083745 A SG2006083745 A SG 2006083745A SG 134208 A1 SG134208 A1 SG 134208A1
Authority
SG
Singapore
Prior art keywords
insulating layer
fabricating
substrate
insulating
insulating layers
Prior art date
Application number
SG200608374-5A
Other languages
English (en)
Inventor
Sebastien Kerdiles
Frederic Allibert
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG134208A1 publication Critical patent/SG134208A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
SG200608374-5A 2006-01-23 2006-11-30 A method of fabricating a composite substrate SG134208A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0600594A FR2896618B1 (fr) 2006-01-23 2006-01-23 Procede de fabrication d'un substrat composite

Publications (1)

Publication Number Publication Date
SG134208A1 true SG134208A1 (en) 2007-08-29

Family

ID=37019044

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200608374-5A SG134208A1 (en) 2006-01-23 2006-11-30 A method of fabricating a composite substrate

Country Status (8)

Country Link
US (2) US7736993B2 (de)
EP (1) EP1811561A1 (de)
JP (1) JP4718425B2 (de)
KR (1) KR100878061B1 (de)
CN (1) CN100530531C (de)
FR (1) FR2896618B1 (de)
SG (1) SG134208A1 (de)
TW (1) TWI355693B (de)

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EP2128891B1 (de) * 2007-02-28 2015-09-02 Shin-Etsu Chemical Co., Ltd. Prozess zum herstellen eines laminierten substrats
FR2919427B1 (fr) * 2007-07-26 2010-12-03 Soitec Silicon On Insulator Structure a reservoir de charges.
TWI437696B (zh) 2007-09-21 2014-05-11 Semiconductor Energy Lab 半導體裝置及其製造方法
FR2922360A1 (fr) 2007-10-12 2009-04-17 Soitec Silicon On Insulator Procede de fabrication d'un substrat de type semi- conducteur sur isolant a plan de masse integre.
JP2011504655A (ja) * 2007-11-23 2011-02-10 エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ 精密な酸化物の溶解
US8093136B2 (en) * 2007-12-28 2012-01-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5412445B2 (ja) * 2008-02-20 2014-02-12 ソイテック 酸化物溶解後の酸化
KR101629193B1 (ko) * 2008-06-26 2016-06-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판의 제작 방법
FR2938118B1 (fr) * 2008-10-30 2011-04-22 Soitec Silicon On Insulator Procede de fabrication d'un empilement de couches minces semi-conductrices
FR2938119B1 (fr) * 2008-10-30 2011-04-22 Soitec Silicon On Insulator Procede de detachement de couches semi-conductrices a basse temperature
US8581228B2 (en) * 2009-01-22 2013-11-12 Bae Systems Information And Electronic Systems Integration Inc. Corner cube enhanced photocathode
US8492292B2 (en) * 2009-06-29 2013-07-23 Applied Materials, Inc. Methods of forming oxide layers on substrates
US8513090B2 (en) * 2009-07-16 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate, and semiconductor device
DE102010027411A1 (de) * 2010-07-15 2012-01-19 Osram Opto Semiconductors Gmbh Halbleiterbauelement, Substrat und Verfahren zur Herstellung einer Halbleiterschichtenfolge
JP2012033689A (ja) * 2010-07-30 2012-02-16 Sumitomo Electric Device Innovations Inc 半導体装置の製造方法
FR2964111B1 (fr) 2010-08-31 2013-01-25 Commissariat Energie Atomique Procede de collage direct entre deux plaques, comprenant une etape de formation d'une couche de protection temporaire a base d'azote
JP2012116741A (ja) * 2010-11-12 2012-06-21 Sumitomo Electric Ind Ltd Ｉｉｉ族窒化物複合基板
JPWO2012111616A1 (ja) * 2011-02-15 2014-07-07 住友電気工業株式会社 保護膜付複合基板、および半導体デバイスの製造方法
US8704306B2 (en) 2011-03-10 2014-04-22 Tsinghua University Strained Ge-on-insulator structure and method for forming the same
US8786017B2 (en) 2011-03-10 2014-07-22 Tsinghua University Strained Ge-on-insulator structure and method for forming the same
US8890209B2 (en) 2011-03-10 2014-11-18 Tsinghua University Strained GE-ON-insulator structure and method for forming the same
WO2012119417A1 (en) * 2011-03-10 2012-09-13 Tsinghua University Strained ge-on-insulator structure and method for forming the same
FR2980636B1 (fr) 2011-09-22 2016-01-08 St Microelectronics Rousset Protection d'un dispositif electronique contre une attaque laser en face arriere, et support semiconducteur correspondant
JP2015502655A (ja) * 2011-11-04 2015-01-22 ザ シラナ グループ プロプライエタリー リミテッドＴｈｅ Ｓｉｌａｎｎａ Ｇｒｏｕｐ Ｐｔｙ Ｌｔｄ シリコン・オン・インシュレータ物質およびそれを製造する方法
WO2013067572A1 (en) * 2011-11-07 2013-05-16 The Silanna Group Pty Ltd A semiconductor-on-insulator structure and process for producing same
CN103151339B (zh) * 2013-02-08 2016-01-20 日月光半导体制造股份有限公司 电容构造及其制作方法
WO2017163722A1 (ja) 2016-03-25 2017-09-28 日本碍子株式会社 接合方法
WO2017163729A1 (ja) * 2016-03-25 2017-09-28 日本碍子株式会社 接合体および弾性波素子
CN107958839B (zh) * 2016-10-18 2020-09-29 上海新昇半导体科技有限公司 晶圆键合方法及其键合装置
CN110945413B (zh) 2017-08-22 2024-06-21 洛克利光子有限公司 光学调制器以及制作光学调制器的方法
EP3936930B1 (de) 2020-07-08 2023-03-08 Imec VZW Monolithischer iii-v-on-silizium-optoelektronischer phasenmodulator mit einem stegwellenleiter

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JPS6338248A (ja) * 1986-08-04 1988-02-18 Hitachi Ltd 半導体装置およびその製造方法
JPH09213916A (ja) * 1996-02-06 1997-08-15 Nippon Telegr & Teleph Corp <Ntt> Ｓｏｉ基板の製造方法
US6028012A (en) * 1996-12-04 2000-02-22 Yale University Process for forming a gate-quality insulating layer on a silicon carbide substrate
TW444266B (en) * 1998-07-23 2001-07-01 Canon Kk Semiconductor substrate and method of producing same
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US20040175901A1 (en) * 1999-02-10 2004-09-09 Commissariat A L'energie Atomique Method for forming an optical silicon layer on a support and use of said method in the production of optical components
EP1087041B1 (de) 1999-03-16 2009-01-07 Shin-Etsu Handotai Co., Ltd Herstellungsverfahren für siliziumwafer und siliziumwafer
TW468212B (en) * 1999-10-25 2001-12-11 Motorola Inc Method for fabricating a semiconductor structure including a metal oxide interface with silicon
JP3943782B2 (ja) * 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
FR2823599B1 (fr) * 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2838865B1 (fr) * 2002-04-23 2005-10-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee
WO2003103057A1 (en) * 2002-05-31 2003-12-11 Advanced Micro Devices, Inc. Diffusion barrier layer in semiconductor substrates to reduce copper contamination from the back side
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US20040187769A1 (en) * 2003-03-27 2004-09-30 Yoshirou Aoki Method of producing SOI wafer
FR2855909B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat
FR2857982B1 (fr) * 2003-07-24 2007-05-18 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
FR2860341B1 (fr) * 2003-09-26 2005-12-30 Soitec Silicon On Insulator Procede de fabrication de structure multicouche a pertes diminuees
KR100526887B1 (ko) * 2004-02-10 2005-11-09 삼성전자주식회사 전계효과 트랜지스터 및 그의 제조방법
FR2867310B1 (fr) * 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
FR2867607B1 (fr) * 2004-03-10 2006-07-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat pour la microelectronique, l'opto-electronique et l'optique avec limitaton des lignes de glissement et substrat correspondant
FR2871172B1 (fr) * 2004-06-03 2006-09-22 Soitec Silicon On Insulator Support d'epitaxie hybride et son procede de fabrication

Also Published As

Publication number Publication date
TW200729356A (en) 2007-08-01
CN100530531C (zh) 2009-08-19
EP1811561A1 (de) 2007-07-25
JP4718425B2 (ja) 2011-07-06
US7977747B2 (en) 2011-07-12
JP2007201429A (ja) 2007-08-09
KR20070077438A (ko) 2007-07-26
TWI355693B (en) 2012-01-01
US7736993B2 (en) 2010-06-15
FR2896618A1 (fr) 2007-07-27
US20100148322A1 (en) 2010-06-17
US20070170503A1 (en) 2007-07-26
KR100878061B1 (ko) 2009-01-14
CN101009203A (zh) 2007-08-01
FR2896618B1 (fr) 2008-05-23

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