FR2964111B1 - Procede de collage direct entre deux plaques, comprenant une etape de formation d'une couche de protection temporaire a base d'azote - Google Patents

Procede de collage direct entre deux plaques, comprenant une etape de formation d'une couche de protection temporaire a base d'azote

Info

Publication number
FR2964111B1
FR2964111B1 FR1003495A FR1003495A FR2964111B1 FR 2964111 B1 FR2964111 B1 FR 2964111B1 FR 1003495 A FR1003495 A FR 1003495A FR 1003495 A FR1003495 A FR 1003495A FR 2964111 B1 FR2964111 B1 FR 2964111B1
Authority
FR
France
Prior art keywords
plates
formation
protective layer
nitrogen protective
collage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1003495A
Other languages
English (en)
Other versions
FR2964111A1 (fr
Inventor
Cioccio Lea Di
Laurent Vandroux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1003495A priority Critical patent/FR2964111B1/fr
Priority to EP11758494.6A priority patent/EP2612353A1/fr
Priority to PCT/FR2011/000483 priority patent/WO2012028792A1/fr
Priority to US13/818,843 priority patent/US9064863B2/en
Publication of FR2964111A1 publication Critical patent/FR2964111A1/fr
Application granted granted Critical
Publication of FR2964111B1 publication Critical patent/FR2964111B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
FR1003495A 2010-08-31 2010-08-31 Procede de collage direct entre deux plaques, comprenant une etape de formation d'une couche de protection temporaire a base d'azote Expired - Fee Related FR2964111B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1003495A FR2964111B1 (fr) 2010-08-31 2010-08-31 Procede de collage direct entre deux plaques, comprenant une etape de formation d'une couche de protection temporaire a base d'azote
EP11758494.6A EP2612353A1 (fr) 2010-08-31 2011-08-31 Procédé de collage direct entre deux plaques, comprenant une étape de formation d'une couche de protection temporaire à base d'azote
PCT/FR2011/000483 WO2012028792A1 (fr) 2010-08-31 2011-08-31 Procédé de collage direct entre deux plaques, comprenant une étape de formation d'une couche de protection temporaire à base d'azote
US13/818,843 US9064863B2 (en) 2010-08-31 2011-08-31 Method for directly adhering two plates together, including a step of forming a temporary protective nitrogen

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1003495A FR2964111B1 (fr) 2010-08-31 2010-08-31 Procede de collage direct entre deux plaques, comprenant une etape de formation d'une couche de protection temporaire a base d'azote

Publications (2)

Publication Number Publication Date
FR2964111A1 FR2964111A1 (fr) 2012-03-02
FR2964111B1 true FR2964111B1 (fr) 2013-01-25

Family

ID=43859729

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1003495A Expired - Fee Related FR2964111B1 (fr) 2010-08-31 2010-08-31 Procede de collage direct entre deux plaques, comprenant une etape de formation d'une couche de protection temporaire a base d'azote

Country Status (4)

Country Link
US (1) US9064863B2 (fr)
EP (1) EP2612353A1 (fr)
FR (1) FR2964111B1 (fr)
WO (1) WO2012028792A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106159114A (zh) * 2015-04-23 2016-11-23 上海和辉光电有限公司 柔性显示器的封装方法
US10892156B2 (en) * 2017-05-08 2021-01-12 Asm Ip Holding B.V. Methods for forming a silicon nitride film on a substrate and related semiconductor device structures

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2896618B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite
EP2084740A1 (fr) * 2006-10-27 2009-08-05 S.O.I.TEC. Silicon on Insulator Technologies S.A. Procédé optimisé de transfert d'une couche mince formée dans un substrat avec groupes de trous
JP2009135430A (ja) * 2007-10-10 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US7842583B2 (en) * 2007-12-27 2010-11-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
US8003483B2 (en) * 2008-03-18 2011-08-23 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8871610B2 (en) * 2008-10-02 2014-10-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

Also Published As

Publication number Publication date
WO2012028792A1 (fr) 2012-03-08
FR2964111A1 (fr) 2012-03-02
US20130217207A1 (en) 2013-08-22
EP2612353A1 (fr) 2013-07-10
US9064863B2 (en) 2015-06-23

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20160429