SG10201905847YA - Memory device scrambling address - Google Patents
Memory device scrambling addressInfo
- Publication number
- SG10201905847YA SG10201905847YA SG10201905847YA SG10201905847YA SG10201905847YA SG 10201905847Y A SG10201905847Y A SG 10201905847YA SG 10201905847Y A SG10201905847Y A SG 10201905847YA SG 10201905847Y A SG10201905847Y A SG 10201905847YA SG 10201905847Y A SG10201905847Y A SG 10201905847YA
- Authority
- SG
- Singapore
- Prior art keywords
- memory device
- device scrambling
- scrambling address
- address
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
- G06F2212/1036—Life time enhancement
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Human Computer Interaction (AREA)
- Dram (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020180085497A KR102091524B1 (ko) | 2018-07-23 | 2018-07-23 | 어드레스를 스크램블하는 메모리 장치 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201905847YA true SG10201905847YA (en) | 2020-02-27 |
Family
ID=69162061
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201905847YA SG10201905847YA (en) | 2018-07-23 | 2019-06-24 | Memory device scrambling address |
Country Status (4)
Country | Link |
---|---|
US (1) | US10957380B2 (zh) |
KR (1) | KR102091524B1 (zh) |
CN (1) | CN110751966B (zh) |
SG (1) | SG10201905847YA (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102471523B1 (ko) * | 2018-04-26 | 2022-11-28 | 에스케이하이닉스 주식회사 | 반도체 집적 회로 장치 및 이를 포함하는 반도체 메모리 시스템 |
KR20200068942A (ko) * | 2018-12-06 | 2020-06-16 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그의 동작 방법 |
EP3675125A1 (en) * | 2018-12-27 | 2020-07-01 | Secure-IC SAS | Device and method for protecting a memory |
KR20210017241A (ko) * | 2019-08-07 | 2021-02-17 | 에스케이하이닉스 주식회사 | 메모리 시스템 |
US11342019B2 (en) | 2019-09-27 | 2022-05-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Compensation word line driver |
US11017879B1 (en) * | 2019-12-20 | 2021-05-25 | Micron Technology, Inc. | Adjustable column address scramble using fuses |
KR20210093521A (ko) * | 2020-01-20 | 2021-07-28 | 삼성전자주식회사 | 고대역폭 메모리 및 이를 포함하는 시스템 |
KR20220095576A (ko) * | 2020-12-30 | 2022-07-07 | 삼성전자주식회사 | 반도체 메모리 장치 및 반도체 메모리 장치의 동작 방법 |
US11670349B2 (en) * | 2021-03-31 | 2023-06-06 | Changxin Memory Technologies, Inc. | Memory circuit, memory precharge control method and device |
KR20220169285A (ko) | 2021-06-18 | 2022-12-27 | 삼성전자주식회사 | 서브 워드라인 구동 회로를 포함하는 메모리 장치 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63177235A (ja) | 1987-01-19 | 1988-07-21 | Fujitsu Ltd | 多次元アクセスメモリ |
JPH10172298A (ja) * | 1996-12-05 | 1998-06-26 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR100253310B1 (ko) * | 1997-08-26 | 2000-05-01 | 김영환 | 반도체 메모리 장치의 프로그램 데이타 보호 회로 |
KR100414207B1 (ko) * | 2001-09-11 | 2004-01-13 | 삼성전자주식회사 | 반도체 메모리 장치 |
KR100567023B1 (ko) * | 2001-12-27 | 2006-04-04 | 매그나칩 반도체 유한회사 | 반도체 메모리의 워드라인 구동 회로 |
KR100479821B1 (ko) * | 2002-05-17 | 2005-03-30 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 리프레쉬 제어회로 및 리프레쉬 제어방법 |
DE10322541A1 (de) | 2003-05-19 | 2004-12-16 | Infineon Technologies Ag | Speicherbaustein mit integrierter Adressscramblereinheit und Verfahren zum Verscrambeln einer Adresse in einem integrierten Speicher |
TWI222598B (en) | 2003-07-09 | 2004-10-21 | Sunplus Technology Co Ltd | Device and method protecting data by scrambling address lines |
KR20060059492A (ko) * | 2004-11-29 | 2006-06-02 | 삼성전자주식회사 | 반도체 메모리 장치 |
JP4326516B2 (ja) | 2005-10-13 | 2009-09-09 | 株式会社ルネサステクノロジ | 半導体記憶装置およびダイナミック型半導体記憶装置 |
US7493467B2 (en) | 2005-12-16 | 2009-02-17 | Intel Corporation | Address scrambling to simplify memory controller's address output multiplexer |
US9170878B2 (en) | 2011-04-11 | 2015-10-27 | Inphi Corporation | Memory buffer with data scrambling and error correction |
KR20130039505A (ko) | 2011-10-12 | 2013-04-22 | 삼성전자주식회사 | 랜덤 코드 발생기를 포함하는 어드레스 변환 회로 및 이를 포함하는 반도체 메모리 장치 |
DE112012006172B4 (de) | 2012-03-30 | 2020-12-03 | Intel Corporation | Generischer Adressen-Scrambler für Speicherschaltungs-Testengine |
US11024352B2 (en) * | 2012-04-10 | 2021-06-01 | Samsung Electronics Co., Ltd. | Memory system for access concentration decrease management and access concentration decrease method |
US9400890B2 (en) | 2012-08-10 | 2016-07-26 | Qualcomm Incorporated | Method and devices for selective RAM scrambling |
KR20140046854A (ko) | 2012-10-11 | 2014-04-21 | 삼성전자주식회사 | Otp 셀 어레이를 구비하는 반도체 메모리 장치 |
KR102128825B1 (ko) * | 2013-12-11 | 2020-07-01 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 동작 방법 |
KR102282971B1 (ko) | 2014-12-05 | 2021-07-29 | 삼성전자주식회사 | 반도체 메모리 장치, 및 상기 반도체 메모리 장치를 포함하는 메모리 시스템 |
US10025747B2 (en) | 2015-05-07 | 2018-07-17 | Samsung Electronics Co., Ltd. | I/O channel scrambling/ECC disassociated communication protocol |
GB2544546B (en) | 2015-11-20 | 2020-07-15 | Advanced Risc Mach Ltd | Dynamic memory scrambling |
CN105516288B (zh) * | 2015-12-01 | 2019-05-21 | 盛科网络(苏州)有限公司 | 采用单根Serdes扩展物理接口的装置、其控制方法及控制系统 |
JP6181218B2 (ja) * | 2016-02-09 | 2017-08-16 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
FR3055734B1 (fr) * | 2016-09-05 | 2018-09-28 | STMicroelectronics (Grand Ouest) SAS | Procede et dispositif d'attenuation d'interferences electromagnetiques lors d'un transfert de donnees depuis ou vers une memoire. |
-
2018
- 2018-07-23 KR KR1020180085497A patent/KR102091524B1/ko active IP Right Grant
-
2019
- 2019-03-29 US US16/369,034 patent/US10957380B2/en active Active
- 2019-06-24 CN CN201910548866.9A patent/CN110751966B/zh active Active
- 2019-06-24 SG SG10201905847YA patent/SG10201905847YA/en unknown
Also Published As
Publication number | Publication date |
---|---|
US10957380B2 (en) | 2021-03-23 |
KR102091524B1 (ko) | 2020-03-23 |
CN110751966B (zh) | 2024-05-24 |
US20200027497A1 (en) | 2020-01-23 |
KR20200010884A (ko) | 2020-01-31 |
CN110751966A (zh) | 2020-02-04 |
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