RU2018113432A - Способ изготовления составной подложки из sic - Google Patents
Способ изготовления составной подложки из sic Download PDFInfo
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- RU2018113432A RU2018113432A RU2018113432A RU2018113432A RU2018113432A RU 2018113432 A RU2018113432 A RU 2018113432A RU 2018113432 A RU2018113432 A RU 2018113432A RU 2018113432 A RU2018113432 A RU 2018113432A RU 2018113432 A RU2018113432 A RU 2018113432A
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- Prior art keywords
- sic
- substrate
- layer
- composite
- manufacturing
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- 239000000758 substrate Substances 0.000 title claims 18
- 239000002131 composite material Substances 0.000 title claims 8
- 238000004519 manufacturing process Methods 0.000 title claims 7
- 239000013078 crystal Substances 0.000 claims 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims 4
- 238000003486 chemical etching Methods 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 230000032798 delamination Effects 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2011—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate the substrate being of crystalline insulating material, e.g. sapphire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/02447—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02529—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Materials Engineering (AREA)
Claims (6)
1. Способ изготовления составной подложки из SiC, содержащий монокристаллический слой SiC на поликристаллической подложке из SiC, причем способ содержит следующие этапы в таком порядке: обеспечение монокристаллического слоя SiC на передней стороне опорной подложки, которая выполнена из кремния и имеет пленку оксида кремния на передней и задней своих сторонах, с получением носителя монокристаллического слоя SiC; удаление некоторой или всей толщины пленки оксида кремния по некоторой области или всей задней стороне опорной подложки в носителе монокристаллического слоя SiC с тем, чтобы придать коробление носителю монокристаллического слоя SiC; осаждение поликристаллического SiC на монокристаллический слой SiC путем химического осаждения из паровой фазы с образованием поликристаллической подложки из SiC; и физическое и/или химическое удаление опорной подложки.
2. Способ изготовления составной подложки из SiC по п. 1, в котором пленка оксида кремния опорной подложки представляет собой термооксидную пленку.
3. Способ изготовления составной подложки из SiC по п. 1 или 2, в котором некоторую часть или всю пленку оксида кремния по всей задней стороне опорной подложки в носителе монокристаллического слоя SiC удаляют химическим травлением.
4. Способ изготовления составной подложки из SiC по любому из пп. 1-3, в котором монокристаллический слой SiC обеспечивают путем перенесения на опорную подложку монокристаллической тонкой пленки SiC, отслоенной от монокристаллической подложки из SiC путем расслаивания с помощью ионной имплантации.
5. Способ изготовления составной подложки из SiC по любому из пп. 1-3, в котором монокристаллический слой SiC обеспечивают путем гетероэпитаксиального выращивания SiC на опорной подложке.
6. Способ изготовления составной подложки из SiC по любому из пп. 1-5, в котором составная подложка из SiC имеет величину прогиба, которая задана в диапазоне от -50 мкм до +50 мкм.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015-181908 | 2015-09-15 | ||
JP2015181908A JP6515757B2 (ja) | 2015-09-15 | 2015-09-15 | SiC複合基板の製造方法 |
PCT/JP2016/076537 WO2017047508A1 (ja) | 2015-09-15 | 2016-09-09 | SiC複合基板の製造方法 |
Publications (3)
Publication Number | Publication Date |
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RU2018113432A true RU2018113432A (ru) | 2019-10-16 |
RU2018113432A3 RU2018113432A3 (ru) | 2020-02-20 |
RU2721306C2 RU2721306C2 (ru) | 2020-05-18 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
RU2018113432A RU2721306C2 (ru) | 2015-09-15 | 2016-09-09 | Способ изготовления составной подложки из sic |
Country Status (7)
Country | Link |
---|---|
US (1) | US10431460B2 (ru) |
EP (1) | EP3352197B1 (ru) |
JP (1) | JP6515757B2 (ru) |
CN (1) | CN108140541B (ru) |
RU (1) | RU2721306C2 (ru) |
TW (1) | TWI738665B (ru) |
WO (1) | WO2017047508A1 (ru) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017175799A1 (ja) * | 2016-04-05 | 2017-10-12 | 株式会社サイコックス | 多結晶SiC基板およびその製造方法 |
CN112908839B (zh) * | 2019-12-03 | 2021-10-01 | 上海积塔半导体有限公司 | 减少碳化硅晶圆弯曲度的方法 |
CN115279956A (zh) * | 2019-12-27 | 2022-11-01 | 沃孚半导体公司 | 大直径碳化硅晶片 |
JP6818964B1 (ja) * | 2020-06-01 | 2021-01-27 | 三菱電機株式会社 | 複合基板、複合基板の製造方法、半導体装置および半導体装置の製造方法 |
CN112382559B (zh) * | 2020-11-13 | 2024-06-11 | 中国科学院上海微系统与信息技术研究所 | 一种异质薄膜结构及其制备方法 |
CN116745886A (zh) * | 2021-01-25 | 2023-09-12 | 罗姆股份有限公司 | 半导体衬底及其制造方法和半导体器件 |
CN114959899B (zh) * | 2022-04-13 | 2024-08-06 | 北京青禾晶元半导体科技有限责任公司 | 一种碳化硅复合基板及其制备方法 |
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JPH0897142A (ja) * | 1994-09-26 | 1996-04-12 | Mitsubishi Materials Corp | 半導体基板及びその製造方法 |
JP3003027B2 (ja) * | 1997-06-25 | 2000-01-24 | 日本ピラー工業株式会社 | 単結晶SiCおよびその製造方法 |
US6153166A (en) * | 1997-06-27 | 2000-11-28 | Nippon Pillar Packing Co., Ltd. | Single crystal SIC and a method of producing the same |
JP3043675B2 (ja) * | 1997-09-10 | 2000-05-22 | 日本ピラー工業株式会社 | 単結晶SiC及びその製造方法 |
JP3043689B2 (ja) * | 1997-11-17 | 2000-05-22 | 日本ピラー工業株式会社 | 単結晶SiC及びその製造方法 |
JPH11345954A (ja) * | 1998-05-29 | 1999-12-14 | Shin Etsu Handotai Co Ltd | 半導体基板及びその製造方法 |
JP3087070B1 (ja) * | 1999-08-24 | 2000-09-11 | 日本ピラー工業株式会社 | 半導体デバイス製作用単結晶SiC複合素材及びその製造方法 |
FR2817394B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
FR2817395B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
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JP2005228806A (ja) * | 2004-02-10 | 2005-08-25 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法 |
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JP6061251B2 (ja) | 2013-07-05 | 2017-01-18 | 株式会社豊田自動織機 | 半導体基板の製造方法 |
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2015
- 2015-09-15 JP JP2015181908A patent/JP6515757B2/ja active Active
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2016
- 2016-09-09 WO PCT/JP2016/076537 patent/WO2017047508A1/ja active Application Filing
- 2016-09-09 US US15/759,578 patent/US10431460B2/en active Active
- 2016-09-09 RU RU2018113432A patent/RU2721306C2/ru active
- 2016-09-09 EP EP16846379.2A patent/EP3352197B1/en active Active
- 2016-09-09 CN CN201680052889.5A patent/CN108140541B/zh active Active
- 2016-09-13 TW TW105129826A patent/TWI738665B/zh active
Also Published As
Publication number | Publication date |
---|---|
RU2018113432A3 (ru) | 2020-02-20 |
US10431460B2 (en) | 2019-10-01 |
EP3352197A1 (en) | 2018-07-25 |
RU2721306C2 (ru) | 2020-05-18 |
TWI738665B (zh) | 2021-09-11 |
CN108140541B (zh) | 2022-11-11 |
US20190157087A1 (en) | 2019-05-23 |
CN108140541A (zh) | 2018-06-08 |
EP3352197A4 (en) | 2019-05-01 |
TW201724178A (zh) | 2017-07-01 |
WO2017047508A1 (ja) | 2017-03-23 |
EP3352197B1 (en) | 2020-07-29 |
JP6515757B2 (ja) | 2019-05-22 |
JP2017059626A (ja) | 2017-03-23 |
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