NO891581D0 - Fremgangsmaate og anordning for aksessering av sidemodushukommelse i et datamaskinsystem. - Google Patents

Fremgangsmaate og anordning for aksessering av sidemodushukommelse i et datamaskinsystem.

Info

Publication number
NO891581D0
NO891581D0 NO891581A NO891581A NO891581D0 NO 891581 D0 NO891581 D0 NO 891581D0 NO 891581 A NO891581 A NO 891581A NO 891581 A NO891581 A NO 891581A NO 891581 D0 NO891581 D0 NO 891581D0
Authority
NO
Norway
Prior art keywords
memory
cas
memory cycle
column address
computer system
Prior art date
Application number
NO891581A
Other languages
English (en)
Other versions
NO891581L (no
Inventor
Patrick Maurice Bland
Mark Edward Dean
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of NO891581D0 publication Critical patent/NO891581D0/no
Publication of NO891581L publication Critical patent/NO891581L/no

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management
NO89891581A 1988-05-26 1989-04-18 Fremgangsmaate og anordning for aksessering av sidemodushukommelse i et datamaskinsystem. NO891581L (no)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/196,721 US5034917A (en) 1988-05-26 1988-05-26 Computer system including a page mode memory with decreased access time and method of operation thereof

Publications (2)

Publication Number Publication Date
NO891581D0 true NO891581D0 (no) 1989-04-18
NO891581L NO891581L (no) 1989-11-27

Family

ID=22726583

Family Applications (1)

Application Number Title Priority Date Filing Date
NO89891581A NO891581L (no) 1988-05-26 1989-04-18 Fremgangsmaate og anordning for aksessering av sidemodushukommelse i et datamaskinsystem.

Country Status (24)

Country Link
US (1) US5034917A (no)
EP (1) EP0343769B1 (no)
JP (1) JPH06101225B2 (no)
KR (1) KR920010950B1 (no)
CN (1) CN1010809B (no)
AT (1) ATE125058T1 (no)
BE (1) BE1003816A4 (no)
BR (1) BR8902399A (no)
CA (1) CA1319201C (no)
DE (2) DE68923403T2 (no)
DK (1) DK189589A (no)
ES (1) ES2075045T3 (no)
FI (1) FI95971C (no)
GB (1) GB2219418A (no)
HK (1) HK23896A (no)
IT (1) IT1230189B (no)
MX (1) MX167244B (no)
MY (1) MY104737A (no)
NL (1) NL8901237A (no)
NO (1) NO891581L (no)
NZ (1) NZ228610A (no)
PH (1) PH30402A (no)
PT (1) PT90631B (no)
SE (1) SE8901304L (no)

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JPH07248963A (ja) * 1994-03-08 1995-09-26 Nec Corp Ｄｒａｍ制御装置
JPH08314795A (ja) * 1994-05-19 1996-11-29 Hitachi Ltd 記憶装置の読み出し回路及び記憶システム
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US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
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US6643752B1 (en) * 1999-12-09 2003-11-04 Rambus Inc. Transceiver with latency alignment circuitry
US7017002B2 (en) * 2000-01-05 2006-03-21 Rambus, Inc. System featuring a master device, a buffer device and a plurality of integrated circuit memory devices
US6502161B1 (en) * 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US7266634B2 (en) * 2000-01-05 2007-09-04 Rambus Inc. Configurable width buffered module having flyby elements
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US7404032B2 (en) * 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US20050010737A1 (en) * 2000-01-05 2005-01-13 Fred Ware Configurable width buffered module having splitter elements
US6829184B2 (en) * 2002-01-28 2004-12-07 Intel Corporation Apparatus and method for encoding auto-precharge
US7315928B2 (en) * 2005-02-03 2008-01-01 Mediatek Incorporation Apparatus and related method for accessing page mode flash memory
US8607328B1 (en) 2005-03-04 2013-12-10 David Hodges Methods and systems for automated system support
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Also Published As

Publication number Publication date
FI95971B (fi) 1995-12-29
KR920010950B1 (ko) 1992-12-24
IT8920624A0 (it) 1989-05-24
PH30402A (en) 1997-05-08
CA1319201C (en) 1993-06-15
EP0343769A2 (en) 1989-11-29
HK23896A (en) 1996-02-16
MY104737A (en) 1994-05-31
DE68923403D1 (de) 1995-08-17
GB8904917D0 (en) 1989-04-12
MX167244B (es) 1993-03-11
FI891784A0 (fi) 1989-04-14
SE8901304L (sv) 1989-11-27
IT1230189B (it) 1991-10-18
NZ228610A (en) 1991-03-26
EP0343769B1 (en) 1995-07-12
CN1037983A (zh) 1989-12-13
FI891784A (fi) 1989-11-27
NO891581L (no) 1989-11-27
ATE125058T1 (de) 1995-07-15
US5034917A (en) 1991-07-23
FI95971C (fi) 1996-04-10
NL8901237A (nl) 1989-12-18
JPH06101225B2 (ja) 1994-12-12
KR890017611A (ko) 1989-12-16
BR8902399A (pt) 1990-01-16
DE68923403T2 (de) 1996-03-07
ES2075045T3 (es) 1995-10-01
DK189589A (da) 1989-11-27
DK189589D0 (da) 1989-04-19
GB2219418A (en) 1989-12-06
CN1010809B (zh) 1990-12-12
PT90631B (pt) 1994-10-31
SE8901304D0 (sv) 1989-04-11
EP0343769A3 (en) 1992-04-29
DE3909896A1 (de) 1989-11-30
BE1003816A4 (fr) 1992-06-23
DE3909896C2 (no) 1990-09-20
JPH0223591A (ja) 1990-01-25
PT90631A (pt) 1989-11-30

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