ES2075045T3 - Aparato y metodo para acceder a una memoria en modo pagina en un sistema informatico. - Google Patents

Aparato y metodo para acceder a una memoria en modo pagina en un sistema informatico.

Info

Publication number
ES2075045T3
ES2075045T3 ES89302136T ES89302136T ES2075045T3 ES 2075045 T3 ES2075045 T3 ES 2075045T3 ES 89302136 T ES89302136 T ES 89302136T ES 89302136 T ES89302136 T ES 89302136T ES 2075045 T3 ES2075045 T3 ES 2075045T3
Authority
ES
Spain
Prior art keywords
memory
cas
memory cycle
column address
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89302136T
Other languages
English (en)
Inventor
Patrick Maurice Bland
Mark Edward Dean
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of ES2075045T3 publication Critical patent/ES2075045T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Hardware Redundancy (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)

Abstract

UN COMPUTADOR INCLUYE UNA PAGINA DE MEMORIA EN LA CUAL UNA DIRECCION DE FILA ACOMPAÑADA POR UNA SELECCION DE DIRECCION DE FILA (RAS) ES SEGUIDA POR UNA DIRECCION DE COLUMNA ACOMPAÑADA POR UN SELECCION DE DIRECCION DE COLUMNA (CAS) PARA LEER DATOS DE UNA POSICION DE MEMORIA DURANTE UN CICLO DE MEMORIA. CUANDO, EN UN CICLO DE MEMORIA SIGUIENTE, HAY QUE ACCEDER A OTRA POSICION DE LA MISMA PAGINA, LA DIRECCION DE FIJA Y LA RAS PERMANECEN CONSTANTES Y SE UTILIZA UNA NUEVA DIRECCION DE COLUMNA CON LA CAS QUE ES PRECARGADA CONMUTANDOLA A SU ESTADO DE APAGADA Y LUEGO VOLVIENDO A ENCENDERLA. ESTO SE REALIZA NORMALMENTE AL INICIO DEL SIGUIENTE CICLO DE MEMORIA. EN EL PRESENTE SISTEMA, LOS DATO SON LEIDOS Y ENGANCHADOS POCO DESPUES DE LA LLEGADA DE LA DIRECCION DE COLUMNA Y DE LA CAS AL PRIMERO DE LOS CICLOS DE MEMORIA DE FORMA QUE LA RECARGA DE LA CAS PUEDE TENER LUGAR AL FINAL DEL PRIMER CICLO DE MEMORIA Y ANTES DEL INICIO DEL SIGUIENTE CICLO DE MEMORIA.
ES89302136T 1988-05-26 1989-03-03 Aparato y metodo para acceder a una memoria en modo pagina en un sistema informatico. Expired - Lifetime ES2075045T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/196,721 US5034917A (en) 1988-05-26 1988-05-26 Computer system including a page mode memory with decreased access time and method of operation thereof

Publications (1)

Publication Number Publication Date
ES2075045T3 true ES2075045T3 (es) 1995-10-01

Family

ID=22726583

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89302136T Expired - Lifetime ES2075045T3 (es) 1988-05-26 1989-03-03 Aparato y metodo para acceder a una memoria en modo pagina en un sistema informatico.

Country Status (24)

Country Link
US (1) US5034917A (es)
EP (1) EP0343769B1 (es)
JP (1) JPH06101225B2 (es)
KR (1) KR920010950B1 (es)
CN (1) CN1010809B (es)
AT (1) ATE125058T1 (es)
BE (1) BE1003816A4 (es)
BR (1) BR8902399A (es)
CA (1) CA1319201C (es)
DE (2) DE68923403T2 (es)
DK (1) DK189589A (es)
ES (1) ES2075045T3 (es)
FI (1) FI95971C (es)
GB (1) GB2219418A (es)
HK (1) HK23896A (es)
IT (1) IT1230189B (es)
MX (1) MX167244B (es)
MY (1) MY104737A (es)
NL (1) NL8901237A (es)
NO (1) NO891581L (es)
NZ (1) NZ228610A (es)
PH (1) PH30402A (es)
PT (1) PT90631B (es)
SE (1) SE8901304L (es)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5159679A (en) * 1988-09-09 1992-10-27 Compaq Computer Corporation Computer system with high speed data transfer capabilities
GB9008145D0 (en) * 1989-05-31 1990-06-06 Ibm Microcomputer system employing address offset mechanism to increase the supported cache memory capacity
US5276856A (en) * 1989-09-28 1994-01-04 Pixel Semiconductor, Inc. Memory controller flexible timing control system and method
CA2028085A1 (en) * 1989-11-03 1991-05-04 Dale J. Mayer Paged memory controller
GB2242294B (en) * 1990-03-19 1993-12-22 Apple Computer Memory architecture using page mode writes and single level write buffering
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5247636A (en) * 1990-05-31 1993-09-21 International Business Machines Corporation Digital processor clock circuit
US5301299A (en) * 1990-06-07 1994-04-05 Intel Corporation Optimized write protocol for memory accesses utilizing row and column strobes
US5835945A (en) * 1990-08-06 1998-11-10 Ncr Corporation Memory system with write buffer, prefetch and internal caches
US5278967A (en) * 1990-08-31 1994-01-11 International Business Machines Corporation System for providing gapless data transfer from page-mode dynamic random access memories
US5522064A (en) * 1990-10-01 1996-05-28 International Business Machines Corporation Data processing apparatus for dynamically setting timings in a dynamic memory system
US5274786A (en) * 1990-11-28 1993-12-28 Hewlett-Packard Company Microprocessor memory bus interface for inhibiting relatching of row address portions upon subsequent accesses including a same row address portion
US5265236A (en) * 1990-11-29 1993-11-23 Sun Microsystems, Inc. Method and apparatus for increasing the speed of memory access in a virtual memory system having fast page mode
US5283880A (en) * 1991-01-02 1994-02-01 Compaq Computer Corp. Method of fast buffer copying by utilizing a cache memory to accept a page of source buffer contents and then supplying these contents to a target buffer without causing unnecessary wait states
JP3180362B2 (ja) * 1991-04-04 2001-06-25 日本電気株式会社 情報処理装置
US5353417A (en) * 1991-05-28 1994-10-04 International Business Machines Corp. Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus access
US5253214A (en) * 1991-09-27 1993-10-12 Eastman Kodak Company High-performance memory controller with application-programmable optimization
US5551054A (en) * 1991-11-19 1996-08-27 Adaptec, Inc. Page mode buffer controller for transferring Nb byte pages between a host and buffer memory without interruption except for refresh
US5295247A (en) * 1992-04-17 1994-03-15 Micronics Computers, Inc. Local IDE (integrated drive electronics) bus architecture
WO1993024885A1 (en) * 1992-06-04 1993-12-09 Cabletron Systems, Inc. Adaptive memory controller
DE69323715T2 (de) * 1993-01-21 1999-10-21 Advanced Micro Devices, Inc. Elektronisches Speichersystem und -verfahren
US5732236A (en) * 1993-05-28 1998-03-24 Texas Instruments Incorporated Circuit and method for controlling access to paged DRAM banks with request prioritization and improved precharge schedule
US5640527A (en) * 1993-07-14 1997-06-17 Dell Usa, L.P. Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states
JPH07129456A (ja) * 1993-10-28 1995-05-19 Toshiba Corp コンピュータシステム
US5758107A (en) * 1994-02-14 1998-05-26 Motorola Inc. System for offloading external bus by coupling peripheral device to data processor through interface logic that emulate the characteristics of the external bus
KR970001699B1 (ko) * 1994-03-03 1997-02-13 삼성전자 주식회사 자동프리차아지기능을 가진 동기식 반도체메모리장치
JPH07248963A (ja) * 1994-03-08 1995-09-26 Nec Corp Ｄｒａｍ制御装置
JPH08314795A (ja) * 1994-05-19 1996-11-29 Hitachi Ltd 記憶装置の読み出し回路及び記憶システム
AU703750B2 (en) * 1994-10-14 1999-04-01 Compaq Computer Corporation Easily programmable memory controller which can access different speed memory devices on different cycles
US5701143A (en) * 1995-01-31 1997-12-23 Cirrus Logic, Inc. Circuits, systems and methods for improving row select speed in a row select memory device
USRE36532E (en) * 1995-03-02 2000-01-25 Samsung Electronics Co., Ltd. Synchronous semiconductor memory device having an auto-precharge function
WO1996029652A1 (en) * 1995-03-22 1996-09-26 Ast Research, Inc. Rule-based dram controller
TW388982B (en) * 1995-03-31 2000-05-01 Samsung Electronics Co Ltd Memory controller which executes read and write commands out of order
US5638534A (en) * 1995-03-31 1997-06-10 Samsung Electronics Co., Ltd. Memory controller which executes read and write commands out of order
US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
US5765203A (en) * 1995-12-19 1998-06-09 Seagate Technology, Inc. Storage and addressing method for a buffer memory control system for accessing user and error imformation
US6209071B1 (en) * 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
WO1999019874A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Power control system for synchronous memory device
US6052756A (en) * 1998-01-23 2000-04-18 Oki Electric Industry Co., Ltd. Memory page management
JPH11272606A (ja) * 1998-03-19 1999-10-08 Fujitsu Ltd バス制御装置
US6643752B1 (en) * 1999-12-09 2003-11-04 Rambus Inc. Transceiver with latency alignment circuitry
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US20050010737A1 (en) * 2000-01-05 2005-01-13 Fred Ware Configurable width buffered module having splitter elements
US7266634B2 (en) * 2000-01-05 2007-09-04 Rambus Inc. Configurable width buffered module having flyby elements
US7404032B2 (en) * 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US7010642B2 (en) * 2000-01-05 2006-03-07 Rambus Inc. System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
US6502161B1 (en) * 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US6829184B2 (en) * 2002-01-28 2004-12-07 Intel Corporation Apparatus and method for encoding auto-precharge
US7315928B2 (en) * 2005-02-03 2008-01-01 Mediatek Incorporation Apparatus and related method for accessing page mode flash memory
US8607328B1 (en) 2005-03-04 2013-12-10 David Hodges Methods and systems for automated system support
US8032688B2 (en) * 2005-06-30 2011-10-04 Intel Corporation Micro-tile memory interfaces
US8253751B2 (en) * 2005-06-30 2012-08-28 Intel Corporation Memory controller interface for micro-tiled memory access
US7464225B2 (en) * 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US8878860B2 (en) * 2006-12-28 2014-11-04 Intel Corporation Accessing memory using multi-tiling
CN104238959B (zh) * 2013-06-06 2018-06-19 钰创科技股份有限公司 具有低消耗电流的内存和降低内存消耗电流的方法
CN113361683B (zh) * 2021-05-18 2023-01-10 山东师范大学 一种生物仿脑存储方法及系统

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4239993A (en) * 1978-09-22 1980-12-16 Texas Instruments Incorporated High performance dynamic sense amplifier with active loads
US4318014A (en) * 1979-07-27 1982-03-02 Motorola, Inc. Selective precharge circuit for read-only-memory
JPS5727477A (en) * 1980-07-23 1982-02-13 Nec Corp Memory circuit
JPS57117168A (en) * 1981-01-08 1982-07-21 Nec Corp Memory circuit
GB2112256B (en) * 1981-11-18 1985-11-06 Texas Instruments Ltd Memory apparatus
US4625300A (en) * 1982-12-01 1986-11-25 Texas Instruments Incorporated Single-ended sense amplifier for dynamic memory array
FR2541796B1 (fr) * 1983-02-25 1987-08-21 Texas Instruments France Dispositif permettant de repartir le temps d'acces d'une memoire sur plusieurs utilisateurs
JPS60108953A (ja) * 1983-11-15 1985-06-14 モトローラ・インコーポレーテツド メモリデータバスの多重化方法
US4623986A (en) * 1984-02-23 1986-11-18 Texas Instruments Incorporated Memory access controller having cycle number register for storing the number of column address cycles in a multiple column address/single row address memory access cycle
JPS6142793A (ja) * 1984-08-02 1986-03-01 Seiko Instr & Electronics Ltd 高速メモリシステム
DE3582376D1 (de) * 1984-08-03 1991-05-08 Toshiba Kawasaki Kk Halbleiterspeicheranordnung.
JPH0799616B2 (ja) * 1984-08-30 1995-10-25 三菱電機株式会社 半導体記憶装置
DE3586736T2 (de) * 1984-10-11 1993-02-18 Hitachi Ltd Halbleiterspeicher.
JPS61110394A (ja) * 1984-10-31 1986-05-28 Mitsubishi Electric Corp 半導体記憶装置
US4649522A (en) * 1985-02-11 1987-03-10 At&T Bell Laboratories Fast column access memory
JPS6228994A (ja) * 1985-07-29 1987-02-06 Nec Corp メモリ集積回路
US4658381A (en) * 1985-08-05 1987-04-14 Motorola, Inc. Bit line precharge on a column address change
US4754433A (en) * 1986-09-16 1988-06-28 Ibm Corporation Dynamic ram having multiplexed twin I/O line pairs

Also Published As

Publication number Publication date
GB2219418A (en) 1989-12-06
US5034917A (en) 1991-07-23
DK189589D0 (da) 1989-04-19
NL8901237A (nl) 1989-12-18
EP0343769A3 (en) 1992-04-29
DE68923403T2 (de) 1996-03-07
MX167244B (es) 1993-03-11
DE68923403D1 (de) 1995-08-17
JPH0223591A (ja) 1990-01-25
CA1319201C (en) 1993-06-15
FI95971B (fi) 1995-12-29
EP0343769B1 (en) 1995-07-12
KR890017611A (ko) 1989-12-16
JPH06101225B2 (ja) 1994-12-12
CN1010809B (zh) 1990-12-12
GB8904917D0 (en) 1989-04-12
NZ228610A (en) 1991-03-26
NO891581L (no) 1989-11-27
MY104737A (en) 1994-05-31
PH30402A (en) 1997-05-08
EP0343769A2 (en) 1989-11-29
SE8901304D0 (sv) 1989-04-11
CN1037983A (zh) 1989-12-13
NO891581D0 (no) 1989-04-18
PT90631A (pt) 1989-11-30
HK23896A (en) 1996-02-16
BE1003816A4 (fr) 1992-06-23
IT1230189B (it) 1991-10-18
ATE125058T1 (de) 1995-07-15
DE3909896C2 (es) 1990-09-20
DE3909896A1 (de) 1989-11-30
FI95971C (fi) 1996-04-10
IT8920624A0 (it) 1989-05-24
PT90631B (pt) 1994-10-31
SE8901304L (sv) 1989-11-27
DK189589A (da) 1989-11-27
KR920010950B1 (ko) 1992-12-24
FI891784A0 (fi) 1989-04-14
BR8902399A (pt) 1990-01-16
FI891784A (fi) 1989-11-27

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