DE68923403D1 - Verfahren und Anordnung zur Adressierung eines Seitenmodus-Speichers in einem Computersystem. - Google Patents

Verfahren und Anordnung zur Adressierung eines Seitenmodus-Speichers in einem Computersystem.

Info

Publication number
DE68923403D1
DE68923403D1 DE68923403T DE68923403T DE68923403D1 DE 68923403 D1 DE68923403 D1 DE 68923403D1 DE 68923403 T DE68923403 T DE 68923403T DE 68923403 T DE68923403 T DE 68923403T DE 68923403 D1 DE68923403 D1 DE 68923403D1
Authority
DE
Germany
Prior art keywords
memory
cas
memory cycle
column address
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE68923403T
Other languages
English (en)
Other versions
DE68923403T2 (de
Inventor
Patrick Maurice Bland
Mark Edward Dean
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE68923403D1 publication Critical patent/DE68923403D1/de
Application granted granted Critical
Publication of DE68923403T2 publication Critical patent/DE68923403T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/20—Software design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/70—Software maintenance or management
    • G06F8/71—Version control; Configuration management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Dram (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Hardware Redundancy (AREA)
  • Bus Control (AREA)
DE68923403T 1988-05-26 1989-03-03 Verfahren und Anordnung zur Adressierung eines Seitenmodus-Speichers in einem Computersystem. Expired - Lifetime DE68923403T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/196,721 US5034917A (en) 1988-05-26 1988-05-26 Computer system including a page mode memory with decreased access time and method of operation thereof

Publications (2)

Publication Number Publication Date
DE68923403D1 true DE68923403D1 (de) 1995-08-17
DE68923403T2 DE68923403T2 (de) 1996-03-07

Family

ID=22726583

Family Applications (2)

Application Number Title Priority Date Filing Date
DE68923403T Expired - Lifetime DE68923403T2 (de) 1988-05-26 1989-03-03 Verfahren und Anordnung zur Adressierung eines Seitenmodus-Speichers in einem Computersystem.
DE3909896A Granted DE3909896A1 (de) 1988-05-26 1989-03-25 Vorrichtung und verfahren fuer den zugriff zu in einem seitenspeicher gespeicherten daten

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE3909896A Granted DE3909896A1 (de) 1988-05-26 1989-03-25 Vorrichtung und verfahren fuer den zugriff zu in einem seitenspeicher gespeicherten daten

Country Status (24)

Country Link
US (1) US5034917A (de)
EP (1) EP0343769B1 (de)
JP (1) JPH06101225B2 (de)
KR (1) KR920010950B1 (de)
CN (1) CN1010809B (de)
AT (1) ATE125058T1 (de)
BE (1) BE1003816A4 (de)
BR (1) BR8902399A (de)
CA (1) CA1319201C (de)
DE (2) DE68923403T2 (de)
DK (1) DK189589A (de)
ES (1) ES2075045T3 (de)
FI (1) FI95971C (de)
GB (1) GB2219418A (de)
HK (1) HK23896A (de)
IT (1) IT1230189B (de)
MX (1) MX167244B (de)
MY (1) MY104737A (de)
NL (1) NL8901237A (de)
NO (1) NO891581L (de)
NZ (1) NZ228610A (de)
PH (1) PH30402A (de)
PT (1) PT90631B (de)
SE (1) SE8901304L (de)

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IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
US5247636A (en) * 1990-05-31 1993-09-21 International Business Machines Corporation Digital processor clock circuit
US5301299A (en) * 1990-06-07 1994-04-05 Intel Corporation Optimized write protocol for memory accesses utilizing row and column strobes
US5835945A (en) * 1990-08-06 1998-11-10 Ncr Corporation Memory system with write buffer, prefetch and internal caches
US5278967A (en) * 1990-08-31 1994-01-11 International Business Machines Corporation System for providing gapless data transfer from page-mode dynamic random access memories
US5522064A (en) * 1990-10-01 1996-05-28 International Business Machines Corporation Data processing apparatus for dynamically setting timings in a dynamic memory system
US5274786A (en) * 1990-11-28 1993-12-28 Hewlett-Packard Company Microprocessor memory bus interface for inhibiting relatching of row address portions upon subsequent accesses including a same row address portion
US5265236A (en) * 1990-11-29 1993-11-23 Sun Microsystems, Inc. Method and apparatus for increasing the speed of memory access in a virtual memory system having fast page mode
US5283880A (en) * 1991-01-02 1994-02-01 Compaq Computer Corp. Method of fast buffer copying by utilizing a cache memory to accept a page of source buffer contents and then supplying these contents to a target buffer without causing unnecessary wait states
JP3180362B2 (ja) * 1991-04-04 2001-06-25 日本電気株式会社 情報処理装置
US5353417A (en) * 1991-05-28 1994-10-04 International Business Machines Corp. Personal computer with bus interface controller coupled directly with local processor and input/output data buses and for anticipating memory control changes on arbitration for bus access
US5253214A (en) * 1991-09-27 1993-10-12 Eastman Kodak Company High-performance memory controller with application-programmable optimization
US5551054A (en) * 1991-11-19 1996-08-27 Adaptec, Inc. Page mode buffer controller for transferring Nb byte pages between a host and buffer memory without interruption except for refresh
US5295247A (en) * 1992-04-17 1994-03-15 Micronics Computers, Inc. Local IDE (integrated drive electronics) bus architecture
AU660559B2 (en) * 1992-06-04 1995-06-29 Cabletron Systems, Inc. Adaptive memory controller
EP0607668B1 (de) * 1993-01-21 1999-03-03 Advanced Micro Devices, Inc. Elektronisches Speichersystem und -verfahren
US5732236A (en) * 1993-05-28 1998-03-24 Texas Instruments Incorporated Circuit and method for controlling access to paged DRAM banks with request prioritization and improved precharge schedule
US5640527A (en) * 1993-07-14 1997-06-17 Dell Usa, L.P. Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states
JPH07129456A (ja) * 1993-10-28 1995-05-19 Toshiba Corp コンピュータシステム
US5758107A (en) * 1994-02-14 1998-05-26 Motorola Inc. System for offloading external bus by coupling peripheral device to data processor through interface logic that emulate the characteristics of the external bus
KR970001699B1 (ko) * 1994-03-03 1997-02-13 삼성전자 주식회사 자동프리차아지기능을 가진 동기식 반도체메모리장치
JPH07248963A (ja) * 1994-03-08 1995-09-26 Nec Corp Ｄｒａｍ制御装置
JPH08314795A (ja) * 1994-05-19 1996-11-29 Hitachi Ltd 記憶装置の読み出し回路及び記憶システム
AU703750B2 (en) * 1994-10-14 1999-04-01 Compaq Computer Corporation Easily programmable memory controller which can access different speed memory devices on different cycles
US5701143A (en) * 1995-01-31 1997-12-23 Cirrus Logic, Inc. Circuits, systems and methods for improving row select speed in a row select memory device
USRE36532E (en) * 1995-03-02 2000-01-25 Samsung Electronics Co., Ltd. Synchronous semiconductor memory device having an auto-precharge function
AU5368696A (en) * 1995-03-22 1996-10-08 Ast Research, Inc. Rule-based dram controller
US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
US5638534A (en) * 1995-03-31 1997-06-10 Samsung Electronics Co., Ltd. Memory controller which executes read and write commands out of order
TW388982B (en) * 1995-03-31 2000-05-01 Samsung Electronics Co Ltd Memory controller which executes read and write commands out of order
US5765203A (en) * 1995-12-19 1998-06-09 Seagate Technology, Inc. Storage and addressing method for a buffer memory control system for accessing user and error imformation
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
WO1999019874A1 (en) 1997-10-10 1999-04-22 Rambus Incorporated Power control system for synchronous memory device
US6052756A (en) * 1998-01-23 2000-04-18 Oki Electric Industry Co., Ltd. Memory page management
JPH11272606A (ja) * 1998-03-19 1999-10-08 Fujitsu Ltd バス制御装置
US6643752B1 (en) * 1999-12-09 2003-11-04 Rambus Inc. Transceiver with latency alignment circuitry
US20050010737A1 (en) * 2000-01-05 2005-01-13 Fred Ware Configurable width buffered module having splitter elements
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US7266634B2 (en) * 2000-01-05 2007-09-04 Rambus Inc. Configurable width buffered module having flyby elements
US7404032B2 (en) * 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US6502161B1 (en) 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US7017002B2 (en) * 2000-01-05 2006-03-21 Rambus, Inc. System featuring a master device, a buffer device and a plurality of integrated circuit memory devices
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US6829184B2 (en) * 2002-01-28 2004-12-07 Intel Corporation Apparatus and method for encoding auto-precharge
US7315928B2 (en) * 2005-02-03 2008-01-01 Mediatek Incorporation Apparatus and related method for accessing page mode flash memory
US8607328B1 (en) 2005-03-04 2013-12-10 David Hodges Methods and systems for automated system support
US8032688B2 (en) * 2005-06-30 2011-10-04 Intel Corporation Micro-tile memory interfaces
US8253751B2 (en) * 2005-06-30 2012-08-28 Intel Corporation Memory controller interface for micro-tiled memory access
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7464225B2 (en) * 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US8878860B2 (en) * 2006-12-28 2014-11-04 Intel Corporation Accessing memory using multi-tiling
TWI539468B (zh) * 2013-06-06 2016-06-21 鈺創科技股份有限公司 具有低消耗電流的記憶體和降低記憶體消耗電流的方法
CN113361683B (zh) * 2021-05-18 2023-01-10 山东师范大学 一种生物仿脑存储方法及系统

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US4318014A (en) * 1979-07-27 1982-03-02 Motorola, Inc. Selective precharge circuit for read-only-memory
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JPS60108953A (ja) * 1983-11-15 1985-06-14 モトローラ・インコーポレーテツド メモリデータバスの多重化方法
US4623986A (en) * 1984-02-23 1986-11-18 Texas Instruments Incorporated Memory access controller having cycle number register for storing the number of column address cycles in a multiple column address/single row address memory access cycle
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JPH0799616B2 (ja) * 1984-08-30 1995-10-25 三菱電機株式会社 半導体記憶装置
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US4658381A (en) * 1985-08-05 1987-04-14 Motorola, Inc. Bit line precharge on a column address change
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Also Published As

Publication number Publication date
CN1037983A (zh) 1989-12-13
GB2219418A (en) 1989-12-06
DK189589D0 (da) 1989-04-19
ES2075045T3 (es) 1995-10-01
NL8901237A (nl) 1989-12-18
DK189589A (da) 1989-11-27
MY104737A (en) 1994-05-31
FI891784A0 (fi) 1989-04-14
JPH0223591A (ja) 1990-01-25
CN1010809B (zh) 1990-12-12
ATE125058T1 (de) 1995-07-15
EP0343769A3 (de) 1992-04-29
EP0343769B1 (de) 1995-07-12
SE8901304D0 (sv) 1989-04-11
FI891784A (fi) 1989-11-27
SE8901304L (sv) 1989-11-27
EP0343769A2 (de) 1989-11-29
BE1003816A4 (fr) 1992-06-23
JPH06101225B2 (ja) 1994-12-12
PH30402A (en) 1997-05-08
FI95971B (fi) 1995-12-29
IT8920624A0 (it) 1989-05-24
CA1319201C (en) 1993-06-15
DE3909896A1 (de) 1989-11-30
NO891581L (no) 1989-11-27
KR920010950B1 (ko) 1992-12-24
DE68923403T2 (de) 1996-03-07
KR890017611A (ko) 1989-12-16
DE3909896C2 (de) 1990-09-20
PT90631B (pt) 1994-10-31
GB8904917D0 (en) 1989-04-12
FI95971C (fi) 1996-04-10
MX167244B (es) 1993-03-11
NZ228610A (en) 1991-03-26
NO891581D0 (no) 1989-04-18
BR8902399A (pt) 1990-01-16
PT90631A (pt) 1989-11-30
IT1230189B (it) 1991-10-18
US5034917A (en) 1991-07-23
HK23896A (en) 1996-02-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8330 Complete renunciation