JPS642155A - Write controlling method for external memory device - Google Patents

Write controlling method for external memory device

Info

Publication number
JPS642155A
JPS642155A JP62156558A JP15655887A JPS642155A JP S642155 A JPS642155 A JP S642155A JP 62156558 A JP62156558 A JP 62156558A JP 15655887 A JP15655887 A JP 15655887A JP S642155 A JPS642155 A JP S642155A
Authority
JP
Japan
Prior art keywords
data
storage device
external storage
writing
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62156558A
Other languages
Japanese (ja)
Other versions
JPH012155A (en
Inventor
Kiyoshi Kuno
Haruo Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62156558A priority Critical patent/JPS642155A/en
Publication of JPH012155A publication Critical patent/JPH012155A/en
Publication of JPS642155A publication Critical patent/JPS642155A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To improve the ability and the reliability of write processing by writing attribute data which is easy to be reproduced in an external storage device after temporarily writing it in a cache memory and writing attribute data which is difficult to be reproduced in the cache memory and in the external storage device at the same time.
CONSTITUTION: On a controller 2, a pass 213 which temporarily stores data from a host device 1, a pass 214 which does out the data from the cash memory 209 and writes it in the external memory device 3 later and a selection circuit 204 which can select the data from the host device 1 and the pass writing the data in the external memory 3 in parallel with writing it in the cache memory 209 are provided. When the data sent from the host device is written in the external storage device, the data which is easy to be reproduced is written in the external storage device 3 after temporarily storing it in the cache memory. Then the data which is difficult to be reproduced is written in the cache memory 209 and in the external storage device 3 at the same time. Thus, the write processing for the external storage device is accelerated and the reliability of the write data can be maintained.
COPYRIGHT: (C)1989,JPO&Japio
JP62156558A 1987-06-25 1987-06-25 Write controlling method for external memory device Pending JPS642155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62156558A JPS642155A (en) 1987-06-25 1987-06-25 Write controlling method for external memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62156558A JPS642155A (en) 1987-06-25 1987-06-25 Write controlling method for external memory device

Publications (2)

Publication Number Publication Date
JPH012155A JPH012155A (en) 1989-01-06
JPS642155A true JPS642155A (en) 1989-01-06

Family

ID=15630420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62156558A Pending JPS642155A (en) 1987-06-25 1987-06-25 Write controlling method for external memory device

Country Status (1)

Country Link
JP (1) JPS642155A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5900014A (en) * 1994-12-08 1999-05-04 Ast Research, Inc. External means of overriding and controlling cacheability attribute of selected CPU accesses to monitor instruction and data streams
US5911814A (en) * 1997-07-14 1999-06-15 Mitsubishi Pencil Kabushiki Kaisha Baked color pencil lead and process for producing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5900014A (en) * 1994-12-08 1999-05-04 Ast Research, Inc. External means of overriding and controlling cacheability attribute of selected CPU accesses to monitor instruction and data streams
US5911814A (en) * 1997-07-14 1999-06-15 Mitsubishi Pencil Kabushiki Kaisha Baked color pencil lead and process for producing the same

Similar Documents

Publication Publication Date Title
JPS5725069A (en) Vector data processing equipment
PH30402A (en) Computer system including a page mode memory with decreased access time and method of operation threeof
JPS5755456A (en) Career recording system
CA2218296A1 (en) Method and apparatus for storing and retrieving error check information
JPS642155A (en) Write controlling method for external memory device
JPS55123749A (en) Double recording system of magnetic disc
JPS6476344A (en) Disk cache control system
JPS5534756A (en) Double recording system of magnetic disc device
JPS563485A (en) Buffer memory device
JPS5676821A (en) Power supply method of storage device
JPS5430742A (en) Memory control system
JPS5693156A (en) Floppy disk magazine driving device
JPS5533282A (en) Buffer control system
JPS5794974A (en) Buffer memory control system
JPS53141518A (en) Storing system
JPS57130058A (en) Electrostatic recorder
JPS5644185A (en) Magnetic bubble memory device
JPS5532265A (en) Countermeasure method for power failure of magnetic tape unit
JPS5280111A (en) Magnetic tape controlling system
JPS53141516A (en) Storing system
JPS6446860A (en) Disk cache device
JPS5481809A (en) Magnetic tape memory system
JPS6433703A (en) Read/write circuit for floppy disk device
JPS5539993A (en) Input-output controller
JPS5718168A (en) Key signal generation device