JPS57196332A - Microcomputer interface - Google Patents

Microcomputer interface

Info

Publication number
JPS57196332A
JPS57196332A JP56079556A JP7955681A JPS57196332A JP S57196332 A JPS57196332 A JP S57196332A JP 56079556 A JP56079556 A JP 56079556A JP 7955681 A JP7955681 A JP 7955681A JP S57196332 A JPS57196332 A JP S57196332A
Authority
JP
Japan
Prior art keywords
signal
address
strobe signal
memory
direct connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56079556A
Other languages
Japanese (ja)
Inventor
Takatoshi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56079556A priority Critical patent/JPS57196332A/en
Publication of JPS57196332A publication Critical patent/JPS57196332A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To realize a direct connection between an active device and a passive device without sacrificing the address space of a memory, by multiplexing the signal to be used for selection of a module through a bus line. CONSTITUTION:An active device 1 puts a chip selection signal CS on an address data line AD, turns on a control strobe signal CTS and informs this to a passive device 2. Then the device 1 produces a load address strobe signal RAS and adds a column address to produce a column address strobe signal CAS when necessary. If this access is carried out in the reading cycle, the read data is obtained from the device 2 after having a delay of the access time to the signal CAS. In the case of the writing cycle, the write enable signal is supplied with the timing equal to the switching of address. Thus the data of the bus AD is written to the memory of the device 2. In such a way, the signal CS is also multiplexed to realize a direct connection between the devices 1 and 2.
JP56079556A 1981-05-26 1981-05-26 Microcomputer interface Pending JPS57196332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56079556A JPS57196332A (en) 1981-05-26 1981-05-26 Microcomputer interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56079556A JPS57196332A (en) 1981-05-26 1981-05-26 Microcomputer interface

Publications (1)

Publication Number Publication Date
JPS57196332A true JPS57196332A (en) 1982-12-02

Family

ID=13693273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56079556A Pending JPS57196332A (en) 1981-05-26 1981-05-26 Microcomputer interface

Country Status (1)

Country Link
JP (1) JPS57196332A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50103947A (en) * 1974-01-14 1975-08-16
JPS5274240A (en) * 1975-12-18 1977-06-22 Hitachi Ltd Lsi data processing system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50103947A (en) * 1974-01-14 1975-08-16
JPS5274240A (en) * 1975-12-18 1977-06-22 Hitachi Ltd Lsi data processing system

Similar Documents

Publication Publication Date Title
ATE240553T1 (en) DEVICE AND METHOD FOR TURNING ON A FUNCTION IN A MULTI-MEMORY MODULE
SE8901304L (en) DEVICE AND PROCEDURE FOR ACCESSING A PAGE MODULE IN A COMPUTER SYSTEM
CA2011518A1 (en) Distributed cache dram chip and control method
KR910005308A (en) Semiconductor memory
KR870010551A (en) Dynamic RAM
KR920013462A (en) Semiconductor memory
ATE283515T1 (en) MEMORY EXPANSION MODULE WITH A VARIETY OF MEMORY BANKS AND A BANK CONTROL CIRCUIT
SE8402598L (en) DATA PROCESSING SYSTEM
KR960005605A (en) Semiconductor memory
WO1986006538A3 (en) Memory control circuit permitting microcomputer system to utilize static and dynamic rams
KR910020728A (en) Data Bus Clamp Circuit of Semiconductor Memory
KR920010624A (en) Semiconductor memory device
MY103962A (en) Multiport memory
KR920022297A (en) Dynamic Random Access Memory Device
JPS57196332A (en) Microcomputer interface
TW329047B (en) Semiconductor integrated circuit device providing DRAM semiconductor circuit device
JPS5720979A (en) Memory control system
JPH0450625B2 (en)
JPS5578365A (en) Memory control unit
KR940026964A (en) Semiconductor memory device
KR880002304Y1 (en) Matrix adress selecting circuit of dram
JPS578980A (en) Memory device
JPS6413658A (en) Dram access control device
KR970051210A (en) Semiconductor memory write method by successive write cycles
JPS5674732A (en) Information processing unit