TW329047B - Semiconductor integrated circuit device providing DRAM semiconductor circuit device - Google Patents

Semiconductor integrated circuit device providing DRAM semiconductor circuit device

Info

Publication number
TW329047B
TW329047B TW086100683A TW86100683A TW329047B TW 329047 B TW329047 B TW 329047B TW 086100683 A TW086100683 A TW 086100683A TW 86100683 A TW86100683 A TW 86100683A TW 329047 B TW329047 B TW 329047B
Authority
TW
Taiwan
Prior art keywords
dram
circuit device
semiconductor integrated
integrated circuit
period
Prior art date
Application number
TW086100683A
Other languages
Chinese (zh)
Inventor
Takaki Noguchi
Satoru Michishita
Shinshi Horiguchi
Masaharu Kubo
Toshio Miyamoto
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW329047B publication Critical patent/TW329047B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present invention relates to a semiconductor integrated circuit device which is capable of accessing DRAM in a logical circuit without any control waiting during DRAM self-fresh period so as to be a high speed data transfer semiconductor integrated circuit device. For a semiconductor integrated circuit device including CPU, microcomputer and fast flash memory chip having memory and peripheral circuit, and logical circuit chip having DRAM and ASIC, the operation for controlling DRAM includes general executable DRAM access motion during general DRAM access period, executable DRAM self-fresh motion during DRAM self-fresh period, DRAM reading/writing signal R/W motion from logical circuit during requesting read/write access period, disarming refreshing, and accessing DRAM logical circuit.
TW086100683A 1996-12-04 1997-01-22 Semiconductor integrated circuit device providing DRAM semiconductor circuit device TW329047B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/003548 WO1998025271A1 (en) 1996-12-04 1996-12-04 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
TW329047B true TW329047B (en) 1998-04-01

Family

ID=14154177

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086100683A TW329047B (en) 1996-12-04 1997-01-22 Semiconductor integrated circuit device providing DRAM semiconductor circuit device

Country Status (3)

Country Link
AU (1) AU1040297A (en)
TW (1) TW329047B (en)
WO (1) WO1998025271A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3962850B2 (en) * 2000-01-20 2007-08-22 カシオ電子工業株式会社 Control device for SDRAM
US7613880B2 (en) 2002-11-28 2009-11-03 Renesas Technology Corp. Memory module, memory system, and information device
US8392650B2 (en) * 2010-04-01 2013-03-05 Intel Corporation Fast exit from self-refresh state of a memory device
US8484410B2 (en) 2010-04-12 2013-07-09 Intel Corporation Method to stagger self refreshes
EP3385857A4 (en) * 2015-11-30 2018-12-26 Pezy Computing K.K. Die and package, and manufacturing method for die and producing method for package
CN115932530B (en) * 2023-01-09 2023-06-02 东莞市兆恒机械有限公司 Method for calibrating semiconductor detection equipment

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3255828B2 (en) * 1994-09-21 2002-02-12 松下電器産業株式会社 Semiconductor integrated circuit
JPH08167703A (en) * 1994-10-11 1996-06-25 Matsushita Electric Ind Co Ltd Semiconductor device, manufacture thereof, memory core chip and memory peripheral circuit chip
JP2915312B2 (en) * 1995-02-10 1999-07-05 インターナショナル・ビジネス・マシーンズ・コーポレイション Semiconductor integrated circuit device
JPH08221313A (en) * 1995-02-14 1996-08-30 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
WO1998025271A1 (en) 1998-06-11
AU1040297A (en) 1998-06-29

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