NO20052450L - Flashminne-arkitektur med avkodingsplan for sletting i sidemodus ved hjelp av NMOS og PMOS radarkoding - Google Patents
Flashminne-arkitektur med avkodingsplan for sletting i sidemodus ved hjelp av NMOS og PMOS radarkodingInfo
- Publication number
- NO20052450L NO20052450L NO20052450A NO20052450A NO20052450L NO 20052450 L NO20052450 L NO 20052450L NO 20052450 A NO20052450 A NO 20052450A NO 20052450 A NO20052450 A NO 20052450A NO 20052450 L NO20052450 L NO 20052450L
- Authority
- NO
- Norway
- Prior art keywords
- local
- flash memory
- global
- sectors
- circuits
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
Landscapes
- Read Only Memory (AREA)
Abstract
Sammendrag Et flashminne har en ny sideslettings-arkitektur som bruker en lokal avkodingsplan i stedet for den globale avkodingsplanen i henhold til kjent teknikk. Den nye arkitekturen sparer mer brikkeplass for minneceller og unngår uønsket sletting, uten at det påvirker lesetiden. I henhold til den lokale avkodingsplanen blir flashminnet partisjonert i sektorer (222, 804). Hver sektor omfatter et antall lokale dekodere (202) og lokalkretser. Lokalkretsene omfatter brytere (302, 304, 306) styrt av de globale dekoderne (802), og disse bryterne virker bare i sletteoperasjon og ikke i leseoperasjon. Lesetiden blir ikke påvirket. Hver lokaldekoder er koblet til en rad (212) av minnematrisen. Hver lokaldekoder omfatter en PMOS-transistor (204) for tilføring av positive spenninger samt to NMOS-transistorer (206, 208) for tilførsel av negative spenninger, slik at en sidesletting oppnås og uselekterte rader kan beskyttes mot uønsket sletting uten ekstra og komplekse kretser. Den globale dekoderen (802, 900, 1000) er plassert utenfor sektorene (804) og sørger for globale signaler(GLOB_SRC_SEL, WS, WSN, SG) til alle sektorer via lokalkretsene, slik at det spares areal.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT002240A ITMI20022240A1 (it) | 2002-10-22 | 2002-10-22 | Architettura di memoria flash con cancellazione di modo |
PCT/US2003/027843 WO2004038727A1 (en) | 2002-10-22 | 2003-09-04 | A flash memory architecture with page mode erase using nmos and pmos row decoding scheme |
Publications (2)
Publication Number | Publication Date |
---|---|
NO20052450L true NO20052450L (no) | 2005-05-20 |
NO20052450D0 NO20052450D0 (no) | 2005-05-20 |
Family
ID=32089010
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NO20052450A NO20052450D0 (no) | 2002-10-22 | 2005-05-20 | Flashminne-arkitektur med avkodingsplan for sletting i sidemodus ved hjelp av NMOS og PMOS radarkoding |
Country Status (11)
Country | Link |
---|---|
US (1) | US6804148B2 (no) |
EP (1) | EP1556865A4 (no) |
JP (1) | JP2006504218A (no) |
KR (1) | KR20050059287A (no) |
CN (1) | CN100530430C (no) |
AU (1) | AU2003265938A1 (no) |
CA (1) | CA2500798A1 (no) |
IT (1) | ITMI20022240A1 (no) |
NO (1) | NO20052450D0 (no) |
TW (1) | TWI317130B (no) |
WO (1) | WO2004038727A1 (no) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6915338B1 (en) * | 2000-10-24 | 2005-07-05 | Microsoft Corporation | System and method providing automatic policy enforcement in a multi-computer service application |
US7319616B2 (en) * | 2003-11-13 | 2008-01-15 | Intel Corporation | Negatively biasing deselected memory cells |
JP4662437B2 (ja) * | 2004-11-30 | 2011-03-30 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
ITMI20050868A1 (it) * | 2005-05-13 | 2006-11-14 | St Microelectronics Srl | Circuito di decodifica di riga |
US7548484B2 (en) * | 2005-09-29 | 2009-06-16 | Hynix Semiconductor Inc. | Semiconductor memory device having column decoder |
US7486587B2 (en) * | 2006-07-31 | 2009-02-03 | Sandisk 3D Llc | Dual data-dependent busses for coupling read/write circuits to a memory array |
US7499366B2 (en) * | 2006-07-31 | 2009-03-03 | Sandisk 3D Llc | Method for using dual data-dependent busses for coupling read/write circuits to a memory array |
US8279704B2 (en) * | 2006-07-31 | 2012-10-02 | Sandisk 3D Llc | Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same |
US7554832B2 (en) * | 2006-07-31 | 2009-06-30 | Sandisk 3D Llc | Passive element memory array incorporating reversible polarity word line and bit line decoders |
US7463546B2 (en) | 2006-07-31 | 2008-12-09 | Sandisk 3D Llc | Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders |
US7593259B2 (en) | 2006-09-13 | 2009-09-22 | Mosaid Technologies Incorporated | Flash multi-level threshold distribution scheme |
KR100776900B1 (ko) * | 2006-10-31 | 2007-11-19 | 주식회사 하이닉스반도체 | 플래시 메모리 소자 및 이를 이용한 프로그램/독출 방법 |
US7414891B2 (en) * | 2007-01-04 | 2008-08-19 | Atmel Corporation | Erase verify method for NAND-type flash memories |
US7882405B2 (en) * | 2007-02-16 | 2011-02-01 | Atmel Corporation | Embedded architecture with serial interface for testing flash memories |
US7577059B2 (en) * | 2007-02-27 | 2009-08-18 | Mosaid Technologies Incorporated | Decoding control with address transition detection in page erase function |
US20080232169A1 (en) * | 2007-03-20 | 2008-09-25 | Atmel Corporation | Nand-like memory array employing high-density nor-like memory devices |
TWI417894B (zh) * | 2007-03-21 | 2013-12-01 | Ibm | 於動態隨機存取記憶體架構之定址期間實施省電之結構及方法 |
US7577029B2 (en) * | 2007-05-04 | 2009-08-18 | Mosaid Technologies Incorporated | Multi-level cell access buffer with dual function |
US9588883B2 (en) | 2011-09-23 | 2017-03-07 | Conversant Intellectual Property Management Inc. | Flash memory system |
JP5908803B2 (ja) * | 2012-06-29 | 2016-04-26 | 株式会社フローディア | 不揮発性半導体記憶装置 |
US8737137B1 (en) | 2013-01-22 | 2014-05-27 | Freescale Semiconductor, Inc. | Flash memory with bias voltage for word line/row driver |
KR102210520B1 (ko) | 2013-12-19 | 2021-02-02 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그것의 소거 방법 |
FR3029000B1 (fr) * | 2014-11-24 | 2017-12-22 | Stmicroelectronics Rousset | Dispositif de memoire non volatile compact |
US11087207B2 (en) * | 2018-03-14 | 2021-08-10 | Silicon Storage Technology, Inc. | Decoders for analog neural memory in deep learning artificial neural network |
US10482968B1 (en) * | 2018-11-22 | 2019-11-19 | Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. | Local x-decoder and related memory system |
CN109448772B (zh) * | 2018-11-28 | 2024-05-28 | 合肥博雅半导体有限公司 | 一种减少电压差的存储器字线选择电路及芯片和存储器 |
US11114143B2 (en) * | 2019-02-22 | 2021-09-07 | Intel Corporation | Bipolar decoder for crosspoint memory cells |
CN112151095A (zh) | 2019-06-26 | 2020-12-29 | 北京知存科技有限公司 | 存算一体芯片、存储单元阵列结构 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5438573A (en) * | 1991-09-13 | 1995-08-01 | Sundisk Corporation | Flash EEPROM array data and header file structure |
US5661683A (en) * | 1996-02-05 | 1997-08-26 | Integrated Silicon Solution Inc. | On-chip positive and negative high voltage wordline x-decoding for EPROM/FLASH |
US5959891A (en) | 1996-08-16 | 1999-09-28 | Altera Corporation | Evaluation of memory cell characteristics |
US5956268A (en) * | 1997-02-12 | 1999-09-21 | Hyundai Electronics America | Nonvolatile memory structure |
US5886923A (en) * | 1997-10-27 | 1999-03-23 | Integrated Silicon Solution Inc. | Local row decoder for sector-erase fowler-nordheim tunneling based flash memory |
US5903497A (en) | 1997-12-22 | 1999-05-11 | Programmable Microelectronics Corporation | Integrated program verify page buffer |
US6359810B1 (en) | 1998-03-13 | 2002-03-19 | Atmel Corporation | Page mode erase in a flash memory array |
US5991198A (en) * | 1998-04-02 | 1999-11-23 | Nexflash Technologies, Inc. | Local row decoder and associated control logic for fowler-nordheim tunneling based flash memory |
US5999451A (en) | 1998-07-13 | 1999-12-07 | Macronix International Co., Ltd. | Byte-wide write scheme for a page flash device |
EP1028433B1 (en) | 1999-02-10 | 2004-04-28 | SGS-THOMSON MICROELECTRONICS s.r.l. | Nonvolatile memory and reading method therefor |
DE69923548D1 (de) | 1999-06-22 | 2005-03-10 | St Microelectronics Srl | Flashkompatibler EEPROM Speicher |
KR100308480B1 (ko) * | 1999-07-13 | 2001-11-01 | 윤종용 | 고집적화에 적합한 행 디코딩 구조를 갖는 플래시 메모리 장치 |
JP3859912B2 (ja) | 1999-09-08 | 2006-12-20 | 株式会社東芝 | 不揮発性半導体記憶装置 |
TW540053B (en) | 2000-07-13 | 2003-07-01 | Samsung Electronics Co Ltd | Row decoder of a NOR-type flash memory device |
KR100381962B1 (ko) * | 2000-08-07 | 2003-05-01 | 삼성전자주식회사 | 비휘발성 메모리 장치의 로우 디코더 |
-
2002
- 2002-10-22 IT IT002240A patent/ITMI20022240A1/it unknown
-
2003
- 2003-01-27 US US10/352,734 patent/US6804148B2/en not_active Expired - Lifetime
- 2003-09-04 JP JP2004546724A patent/JP2006504218A/ja not_active Withdrawn
- 2003-09-04 AU AU2003265938A patent/AU2003265938A1/en not_active Abandoned
- 2003-09-04 WO PCT/US2003/027843 patent/WO2004038727A1/en active Application Filing
- 2003-09-04 KR KR1020057006997A patent/KR20050059287A/ko active IP Right Grant
- 2003-09-04 EP EP03809517A patent/EP1556865A4/en not_active Withdrawn
- 2003-09-04 CN CNB038243342A patent/CN100530430C/zh not_active Expired - Fee Related
- 2003-09-04 CA CA002500798A patent/CA2500798A1/en not_active Abandoned
- 2003-10-02 TW TW092127289A patent/TWI317130B/zh not_active IP Right Cessation
-
2005
- 2005-05-20 NO NO20052450A patent/NO20052450D0/no unknown
Also Published As
Publication number | Publication date |
---|---|
CN1689115A (zh) | 2005-10-26 |
KR20050059287A (ko) | 2005-06-17 |
EP1556865A1 (en) | 2005-07-27 |
CN100530430C (zh) | 2009-08-19 |
NO20052450D0 (no) | 2005-05-20 |
JP2006504218A (ja) | 2006-02-02 |
US20040076037A1 (en) | 2004-04-22 |
AU2003265938A1 (en) | 2004-05-13 |
ITMI20022240A1 (it) | 2004-04-23 |
US6804148B2 (en) | 2004-10-12 |
TWI317130B (en) | 2009-11-11 |
EP1556865A4 (en) | 2010-06-30 |
WO2004038727A1 (en) | 2004-05-06 |
TW200409126A (en) | 2004-06-01 |
CA2500798A1 (en) | 2004-05-06 |
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