NL193394C - Werkwijze voor het vervaardigen van geïntegreerde structuren die niet- vluchtige geheugencellen en bijbehorende transistoren omvatten. - Google Patents
Werkwijze voor het vervaardigen van geïntegreerde structuren die niet- vluchtige geheugencellen en bijbehorende transistoren omvatten. Download PDFInfo
- Publication number
- NL193394C NL193394C NL8503197A NL8503197A NL193394C NL 193394 C NL193394 C NL 193394C NL 8503197 A NL8503197 A NL 8503197A NL 8503197 A NL8503197 A NL 8503197A NL 193394 C NL193394 C NL 193394C
- Authority
- NL
- Netherlands
- Prior art keywords
- regions
- polycrystalline silicon
- layer
- silicon layer
- oxide
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 230000000873 masking effect Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000007796 conventional method Methods 0.000 claims description 2
- 230000006870 function Effects 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 230000001681 protective effect Effects 0.000 claims 1
- 230000000717 retained effect Effects 0.000 claims 1
- 150000003376 silicon Chemical class 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT2373784 | 1984-11-26 | ||
| IT8423737A IT1213249B (it) | 1984-11-26 | 1984-11-26 | Processo per la fabbricazione distrutture integrate includenti celle di memoria non volatili con strati di silicio autoallineati ed associati transistori. |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| NL8503197A NL8503197A (nl) | 1986-06-16 |
| NL193394B NL193394B (nl) | 1999-04-01 |
| NL193394C true NL193394C (nl) | 1999-08-03 |
Family
ID=11209566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| NL8503197A NL193394C (nl) | 1984-11-26 | 1985-11-20 | Werkwijze voor het vervaardigen van geïntegreerde structuren die niet- vluchtige geheugencellen en bijbehorende transistoren omvatten. |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4719184A (ja) |
| JP (1) | JP2525144B2 (ja) |
| DE (1) | DE3540422C2 (ja) |
| FR (1) | FR2573920B1 (ja) |
| GB (1) | GB2167602B (ja) |
| IT (1) | IT1213249B (ja) |
| NL (1) | NL193394C (ja) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1196997B (it) * | 1986-07-25 | 1988-11-25 | Sgs Microelettronica Spa | Processo per realizzare strutture includenti celle di memoria non volatili e2prom con strati di silicio autoallineate transistori associati |
| KR890001957B1 (ko) * | 1986-08-22 | 1989-06-03 | 삼성전자 주식회사 | 디램셀의 제조방법 |
| IT1225873B (it) * | 1987-07-31 | 1990-12-07 | Sgs Microelettrica S P A Catan | Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura. |
| US4859619A (en) * | 1988-07-15 | 1989-08-22 | Atmel Corporation | EPROM fabrication process forming tub regions for high voltage devices |
| JPH02211651A (ja) * | 1989-02-10 | 1990-08-22 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| IT1235690B (it) * | 1989-04-07 | 1992-09-21 | Sgs Thomson Microelectronics | Procedimento di fabbricazione per una matrice di celle eprom organizzate a tovaglia. |
| US5188976A (en) * | 1990-07-13 | 1993-02-23 | Hitachi, Ltd. | Manufacturing method of non-volatile semiconductor memory device |
| US5229631A (en) * | 1990-08-15 | 1993-07-20 | Intel Corporation | Erase performance improvement via dual floating gate processing |
| IT1250233B (it) * | 1991-11-29 | 1995-04-03 | St Microelectronics Srl | Procedimento per la fabbricazione di circuiti integrati in tecnologia mos. |
| CA2107602C (en) * | 1992-10-07 | 2004-01-20 | Andrew Jan Walker | Method of manufacturing an integrated circuit and integrated circuit obtained by this method |
| DE69313816T2 (de) * | 1993-02-11 | 1998-03-26 | St Microelectronics Srl | EEPROM-Zelle und peripherer MOS-Transistor |
| DE69312676T2 (de) * | 1993-02-17 | 1997-12-04 | Sgs Thomson Microelectronics | Prozess zur Herstellung von integrierten Bauelementen einschliesslich nichtvolatiler Speicher und Transistoren mit Tunneloxidschutz |
| DE69631879D1 (de) * | 1996-04-30 | 2004-04-22 | St Microelectronics Srl | Herstellungsverfahren für einen integrierten Dickoxydtransistor |
| EP0902465B1 (en) | 1997-08-27 | 2008-10-15 | STMicroelectronics S.r.l. | Process for manufacturing electronic virtual-ground memory devices |
| JP2003518742A (ja) * | 1999-12-21 | 2003-06-10 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 不揮発性のメモリーセルと周辺部 |
| ITTO20021118A1 (it) * | 2002-12-24 | 2004-06-25 | St Microelectronics Srl | Dispositivo mos e procedimento di fabbricazione di |
| ITTO20021119A1 (it) * | 2002-12-24 | 2004-06-25 | St Microelectronics Srl | Dispositivo mos e procedimento di fabbricazione di |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5591877A (en) * | 1978-12-30 | 1980-07-11 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS56116670A (en) * | 1980-02-20 | 1981-09-12 | Hitachi Ltd | Semiconductor integrated circuit device and manufacture thereof |
| JPS577162A (en) * | 1980-06-17 | 1982-01-14 | Toshiba Corp | Nonvolatile semiconductor memory and manufacture therefor |
| DE3037744A1 (de) * | 1980-10-06 | 1982-05-19 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen einer monolithisch integrierten zwei-transistor-speicherzelle in mos-technik |
| JPS5837701B2 (ja) * | 1980-12-29 | 1983-08-18 | 富士通株式会社 | 半導体装置の製造方法 |
| JPS5852871A (ja) * | 1981-09-25 | 1983-03-29 | Hitachi Ltd | 半導体記憶装置 |
| JPS58196053A (ja) * | 1982-05-11 | 1983-11-15 | Mitsubishi Electric Corp | 半導体装置の製造法 |
| JPS5974677A (ja) * | 1982-10-22 | 1984-04-27 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
| FR2535525A1 (fr) * | 1982-10-29 | 1984-05-04 | Western Electric Co | Procede de fabrication de circuits integres comportant des couches isolantes minces |
-
1984
- 1984-11-26 IT IT8423737A patent/IT1213249B/it active
-
1985
- 1985-11-01 GB GB08526959A patent/GB2167602B/en not_active Expired
- 1985-11-14 DE DE3540422A patent/DE3540422C2/de not_active Expired - Fee Related
- 1985-11-20 NL NL8503197A patent/NL193394C/nl not_active IP Right Cessation
- 1985-11-21 JP JP60259941A patent/JP2525144B2/ja not_active Expired - Fee Related
- 1985-11-25 FR FR8517406A patent/FR2573920B1/fr not_active Expired
-
1987
- 1987-03-06 US US07/022,482 patent/US4719184A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| GB2167602B (en) | 1988-12-07 |
| FR2573920A1 (fr) | 1986-05-30 |
| DE3540422C2 (de) | 2001-04-26 |
| JP2525144B2 (ja) | 1996-08-14 |
| IT1213249B (it) | 1989-12-14 |
| GB8526959D0 (en) | 1985-12-04 |
| NL8503197A (nl) | 1986-06-16 |
| DE3540422A1 (de) | 1986-05-28 |
| JPS61131488A (ja) | 1986-06-19 |
| IT8423737A0 (it) | 1984-11-26 |
| US4719184A (en) | 1988-01-12 |
| FR2573920B1 (fr) | 1988-10-07 |
| NL193394B (nl) | 1999-04-01 |
| GB2167602A (en) | 1986-05-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| NL193394C (nl) | Werkwijze voor het vervaardigen van geïntegreerde structuren die niet- vluchtige geheugencellen en bijbehorende transistoren omvatten. | |
| US5534455A (en) | Method for protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch | |
| US5297082A (en) | Shallow trench source eprom cell | |
| US5804472A (en) | Method of making spacer-type thin-film polysilicon transistor for low-power memory devices | |
| US5899722A (en) | Method of forming dual spacer for self aligned contact integration | |
| KR960019805A (ko) | 비휘발성 메모리셀 및 그 제조방법 | |
| JPS58147072A (ja) | Ｍｏｓ半導体装置の製造方法 | |
| US4532698A (en) | Method of making ultrashort FET using oblique angle metal deposition and ion implantation | |
| CN104465727B (zh) | 分离栅闪存结构的形成方法 | |
| EP0223986B1 (en) | Method for making self-aligned semiconductor structures | |
| US6235585B1 (en) | Method for fabricating flash memory device and peripheral area | |
| US4373250A (en) | Process for fabricating a high capacity memory cell | |
| US5393684A (en) | Method of making thin oxide portions particularly in electrically erasable and programmable read-only memory cells | |
| US4775644A (en) | Zero bird-beak oxide isolation scheme for integrated circuits | |
| JP3297937B2 (ja) | 半導体装置及びその製造方法 | |
| KR950007106A (ko) | 디램(dram)셀 커패시터 제조방법 | |
| JP3783240B2 (ja) | フラッシュメモリの製造方法 | |
| KR0166811B1 (ko) | 스택 커패시터 셀 제조방법 | |
| KR920022552A (ko) | 라운드 트랜치 게이트를 갖는 반도체메모리소자의 제조방법 | |
| KR940016835A (ko) | 반도체 소자의 캐패시터 제조방법 | |
| KR940016924A (ko) | 고속소자용 트랜지스터 제조방법 | |
| KR940003045A (ko) | Dram 셀의 캐패시터 제조방법 | |
| KR910017684A (ko) | 메모리 셀 커패시터 제조방법 | |
| KR940016888A (ko) | 트랜지스터 형성 방법 | |
| JPH0669453A (ja) | 半導体素子 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| BA | A request for search or an international-type search has been filed | ||
| BB | A search report has been drawn up | ||
| BC | A request for examination has been filed | ||
| V1 | Lapsed because of non-payment of the annual fee |
Effective date: 20050601 |