MXPA01008580A - Un paquete de circuito integrado de conexcion de microcircuito de colapso controlado (c4) que tiend dos materiales de subrelleno distintos. - Google Patents

Un paquete de circuito integrado de conexcion de microcircuito de colapso controlado (c4) que tiend dos materiales de subrelleno distintos.

Info

Publication number
MXPA01008580A
MXPA01008580A MXPA01008580A MXPA01008580A MXPA01008580A MX PA01008580 A MXPA01008580 A MX PA01008580A MX PA01008580 A MXPA01008580 A MX PA01008580A MX PA01008580 A MXPA01008580 A MX PA01008580A MX PA01008580 A MXPA01008580 A MX PA01008580A
Authority
MX
Mexico
Prior art keywords
sub
substrate
integrated circuit
filler material
package
Prior art date
Application number
MXPA01008580A
Other languages
English (en)
Spanish (es)
Inventor
Suresh Ramalingam
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of MXPA01008580A publication Critical patent/MXPA01008580A/es

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
MXPA01008580A 1999-03-03 2000-02-08 Un paquete de circuito integrado de conexcion de microcircuito de colapso controlado (c4) que tiend dos materiales de subrelleno distintos. MXPA01008580A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/261,849 US20020014688A1 (en) 1999-03-03 1999-03-03 Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
PCT/US2000/003242 WO2000052756A1 (en) 1999-03-03 2000-02-08 A controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials

Publications (1)

Publication Number Publication Date
MXPA01008580A true MXPA01008580A (es) 2002-04-24

Family

ID=22995146

Family Applications (1)

Application Number Title Priority Date Filing Date
MXPA01008580A MXPA01008580A (es) 1999-03-03 2000-02-08 Un paquete de circuito integrado de conexcion de microcircuito de colapso controlado (c4) que tiend dos materiales de subrelleno distintos.

Country Status (7)

Country Link
US (2) US20020014688A1 (enExample)
JP (1) JP2002538626A (enExample)
KR (1) KR100522383B1 (enExample)
CN (1) CN1191627C (enExample)
AU (1) AU2986000A (enExample)
MX (1) MXPA01008580A (enExample)
WO (1) WO2000052756A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020014688A1 (en) * 1999-03-03 2002-02-07 Suresh Ramalingam Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
US20090279275A1 (en) * 2008-05-09 2009-11-12 Stephen Peter Ayotte Method of attaching an integrated circuit chip to a module
CN102105971B (zh) * 2009-04-24 2013-05-22 松下电器产业株式会社 半导体封装元器件的安装方法和安装结构体
US8686749B2 (en) * 2010-04-30 2014-04-01 International Business Machines Corporation Thermal interface material, test structure and method of use
JP2012049175A (ja) * 2010-08-24 2012-03-08 Toshiba Corp 半導体装置の製造方法
KR20120040536A (ko) 2010-10-19 2012-04-27 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9559064B2 (en) * 2013-12-04 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control in package-on-package structures
US9373559B2 (en) * 2014-03-05 2016-06-21 International Business Machines Corporation Low-stress dual underfill packaging
US9524956B2 (en) 2014-10-31 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method
WO2017180482A1 (en) * 2016-04-11 2017-10-19 Paradromics, Inc. Neural-interface probe and methods of packaging the same
WO2018183967A1 (en) 2017-03-30 2018-10-04 Paradromics, Inc. Patterned microwire bundles and methods of producing the same
WO2019055307A1 (en) * 2017-09-15 2019-03-21 Cryptography Research, Inc. PACKAGING TECHNIQUES FOR REAR MESH CONNECTIVITY
US11075133B2 (en) 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill structure for semiconductor packages and methods of forming the same
CN110660752A (zh) * 2018-06-29 2020-01-07 台湾积体电路制造股份有限公司 半导体装置封装体及其制造方法
US12171995B1 (en) 2021-10-07 2024-12-24 Paradromics, Inc. Methods for improved biocompatibility for human implanted medical devices

Family Cites Families (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322737A (en) 1979-11-20 1982-03-30 Intel Corporation Integrated circuit micropackaging
JPS62169433A (ja) * 1986-01-22 1987-07-25 Fuji Xerox Co Ltd 半導体装置の製造方法
JPS63239827A (ja) 1987-03-27 1988-10-05 Hitachi Ltd 半導体装置
EP0340492A3 (en) * 1988-05-02 1990-07-04 International Business Machines Corporation Conformal sealing and interplanar encapsulation of electronic device structures
JPH0256941A (ja) 1988-08-20 1990-02-26 Matsushita Electric Works Ltd 半導体素子の封止方法
JPH0282633A (ja) * 1988-09-20 1990-03-23 Seiko Epson Corp 半導体素子の実装構造
JPH0340458A (ja) 1989-07-07 1991-02-21 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JPH0639563B2 (ja) 1989-12-15 1994-05-25 株式会社日立製作所 半導体装置の製法
US6020579A (en) * 1997-01-06 2000-02-01 International Business Machines Corporation Microwave applicator having a mechanical means for tuning
US5320250A (en) * 1991-12-02 1994-06-14 Asymptotic Technologies, Inc. Method for rapid dispensing of minute quantities of viscous material
JPH05218137A (ja) * 1992-02-05 1993-08-27 Toshiba Corp 半導体装置の製造方法
US5249101A (en) * 1992-07-06 1993-09-28 International Business Machines Corporation Chip carrier with protective coating for circuitized surface
US5390082A (en) * 1992-07-06 1995-02-14 International Business Machines, Corp. Chip carrier with protective coating for circuitized surface
US5371325A (en) 1992-10-30 1994-12-06 At&T Corp. Insulation system for magnetic devices
US5321583A (en) 1992-12-02 1994-06-14 Intel Corporation Electrically conductive interposer and array package concept for interconnecting to a circuit board
US5371328A (en) 1993-08-20 1994-12-06 International Business Machines Corporation Component rework
JP2774436B2 (ja) 1993-09-07 1998-07-09 リンナイ株式会社 多孔質体
JPH0846098A (ja) * 1994-07-22 1996-02-16 Internatl Business Mach Corp <Ibm> 直接的熱伝導路を形成する装置および方法
US5539153A (en) 1994-08-08 1996-07-23 Hewlett-Packard Company Method of bumping substrates by contained paste deposition
JP3233535B2 (ja) * 1994-08-15 2001-11-26 株式会社東芝 半導体装置及びその製造方法
JPH08153830A (ja) 1994-11-29 1996-06-11 Toshiba Corp 半導体装置およびその製造方法
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
US5811317A (en) * 1995-08-25 1998-09-22 Texas Instruments Incorporated Process for reflow bonding a semiconductor die to a substrate and the product produced by the product
EP1256387B1 (en) * 1995-10-13 2009-02-18 Nordson Corporation Flip chip underfill system and method
EP0778616A3 (en) 1995-12-05 1999-03-31 Lucent Technologies Inc. Method of packaging devices with a gel medium confined by a rim member
US5766982A (en) 1996-03-07 1998-06-16 Micron Technology, Inc. Method and apparatus for underfill of bumped or raised die
JP3235454B2 (ja) 1996-03-29 2001-12-04 松下電器産業株式会社 電子部品の接合方法
US5751556A (en) 1996-03-29 1998-05-12 Intel Corporation Method and apparatus for reducing warpage of an assembly substrate
US5821456A (en) 1996-05-01 1998-10-13 Motorola, Inc. Microelectronic assembly including a decomposable encapsulant, and method for forming and reworking same
JP2891184B2 (ja) 1996-06-13 1999-05-17 日本電気株式会社 半導体装置及びその製造方法
JPH1055832A (ja) 1996-08-08 1998-02-24 Yazaki Corp 圧接端子
US5804771A (en) 1996-09-26 1998-09-08 Intel Corporation Organic substrate (PCB) slip plane "stress deflector" for flip chip deivces
JP2848357B2 (ja) * 1996-10-02 1999-01-20 日本電気株式会社 半導体装置の実装方法およびその実装構造
US5942805A (en) 1996-12-20 1999-08-24 Intel Corporation Fiducial for aligning an integrated circuit die
EP0896368A4 (en) * 1997-01-23 2000-03-01 Seiko Epson Corp FILM CARRIER TAPE, SEMICONDUCTOR ARRANGEMENT, SEMICONDUCTOR, MANUFACTURING METHOD FOR IT, MOUNTING PLATE AND SEMICONDUCTOR DEVICE
US5891753A (en) 1997-01-24 1999-04-06 Micron Technology, Inc. Method and apparatus for packaging flip chip bare die on printed circuit boards
US5990552A (en) 1997-02-07 1999-11-23 Intel Corporation Apparatus for attaching a heat sink to the back side of a flip chip package
JP3704864B2 (ja) * 1997-02-12 2005-10-12 株式会社デンソー 半導体素子の実装構造
US5815372A (en) 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US6104093A (en) * 1997-04-24 2000-08-15 International Business Machines Corporation Thermally enhanced and mechanically balanced flip chip package and method of forming
JPH1154884A (ja) 1997-08-06 1999-02-26 Nec Corp 半導体装置の実装構造
US6367150B1 (en) * 1997-09-05 2002-04-09 Northrop Grumman Corporation Solder flux compatible with flip-chip underfill material
US6121358A (en) * 1997-09-22 2000-09-19 The Dexter Corporation Hydrophobic vinyl monomers, formulations containing same, and uses therefor
US6166434A (en) * 1997-09-23 2000-12-26 Lsi Logic Corporation Die clip assembly for semiconductor package
JP3482115B2 (ja) * 1997-10-13 2003-12-22 東レ・ダウコーニング・シリコーン株式会社 硬化性シリコーン組成物および電子部品
US5919329A (en) * 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6049122A (en) 1997-10-16 2000-04-11 Fujitsu Limited Flip chip mounting substrate with resin filled between substrate and semiconductor chip
US5998242A (en) 1997-10-27 1999-12-07 Lsi Logic Corporation Vacuum assisted underfill process and apparatus for semiconductor package fabrication
KR200247909Y1 (ko) 1997-11-03 2001-12-17 최원철 결착해지가 용이한 밴드케이블
US6204564B1 (en) * 1997-11-21 2001-03-20 Rohm Co., Ltd. Semiconductor device and method for making the same
US5917702A (en) 1997-11-26 1999-06-29 Intel Corporation Corner heat sink which encloses an integrated circuit of a ball grid array integrated circuit package
US6049124A (en) 1997-12-10 2000-04-11 Intel Corporation Semiconductor package
US5936304A (en) 1997-12-10 1999-08-10 Intel Corporation C4 package die backside coating
US5965937A (en) 1997-12-15 1999-10-12 Intel Corporation Thermal interface attach mechanism for electrical packages
US5920120A (en) 1997-12-19 1999-07-06 Intel Corporation Assembly for dissipatating heat from a semiconductor chip wherein a stress on the semiconductor chip due to a thermally conductive member is partially relieved
US5991161A (en) 1997-12-19 1999-11-23 Intel Corporation Multi-chip land grid array carrier
US6201301B1 (en) * 1998-01-21 2001-03-13 Lsi Logic Corporation Low cost thermally enhanced flip chip BGA
US6017983A (en) * 1998-01-29 2000-01-25 Alpha Metals, Inc. Color indicator for completion of polymerization for thermosets
US5953814A (en) * 1998-02-27 1999-09-21 Delco Electronics Corp. Process for producing flip chip circuit board assembly exhibiting enhanced reliability
US6011301A (en) * 1998-06-09 2000-01-04 Stmicroelectronics, Inc. Stress reduction for flip chip package
US6057381A (en) 1998-07-02 2000-05-02 National Starch And Chemical Investment Holding Corporation Method of making an electronic component using reworkable underfill encapsulants
US6238948B1 (en) * 1999-03-03 2001-05-29 Intel Corporation Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material
US6331446B1 (en) * 1999-03-03 2001-12-18 Intel Corporation Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state
US20020014688A1 (en) * 1999-03-03 2002-02-07 Suresh Ramalingam Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials

Also Published As

Publication number Publication date
CN1350702A (zh) 2002-05-22
JP2002538626A (ja) 2002-11-12
KR100522383B1 (ko) 2005-10-19
WO2000052756A1 (en) 2000-09-08
CN1191627C (zh) 2005-03-02
AU2986000A (en) 2000-09-21
US7141448B2 (en) 2006-11-28
US20020014688A1 (en) 2002-02-07
US20020017728A1 (en) 2002-02-14
KR20010108306A (ko) 2001-12-07

Similar Documents

Publication Publication Date Title
MXPA01008580A (es) Un paquete de circuito integrado de conexcion de microcircuito de colapso controlado (c4) que tiend dos materiales de subrelleno distintos.
MXPA01008691A (es) Un paquete de circuito integrado de conexion de microcircuito de colapso controlado (c4) que tiene un rellenador el cual sella un material de subrelleno.
JP3118187B2 (ja) 再加工可能な電子デバイス及び形成方法
KR100412156B1 (ko) 반도체장치 및 그 제조방법
MXPA01008692A (es) Una linea de proceso para subrellenar un paquete de circuito integrado de conexion de microcircuito de colapso controlado (c4) con un material de subrelleno que es calentado hasta un estado de gelificacion parcial.
CN1239059C (zh) 制造互连组件的方法及设备
US6259155B1 (en) Polymer enhanced column grid array
US20160247776A1 (en) Electronic apparatus and method for fabricating the same
CN105722308A (zh) 制造具有热的金属化通孔的线路装置
CN202585401U (zh) 半导体封装构造
MXPA01008581A (es) Una linea de proceso para subrellenar un paquete de circuito integrado de conexion de microcircuito de colapso controlado (c4).
US6649833B1 (en) Negative volume expansion lead-free electrical connection
JP6936595B2 (ja) 半導体装置
KR100498675B1 (ko) 두 가지 다른 하부 충전 재료를 갖는 붕괴 제어형 칩접속(ｃ4) 집적회로 패키지
JPH09260433A (ja) 半導体装置の製法およびそれによって得られた半導体装置
JPH0228349A (ja) 窒化アルミニウムパッケージおよびその製造方法
JPH0483343A (ja) 半導体集積回路装置
HK1118952B (en) Low profile ball grid array (bga) package with exposed die and method of making same

Legal Events

Date Code Title Description
FG Grant or registration
MM Annulment or lapse due to non-payment of fees