KR970071019A - 실시간 데이터 관측 방법 및 장치 - Google Patents
실시간 데이터 관측 방법 및 장치 Download PDFInfo
- Publication number
- KR970071019A KR970071019A KR1019970012998A KR19970012998A KR970071019A KR 970071019 A KR970071019 A KR 970071019A KR 1019970012998 A KR1019970012998 A KR 1019970012998A KR 19970012998 A KR19970012998 A KR 19970012998A KR 970071019 A KR970071019 A KR 970071019A
- Authority
- KR
- South Korea
- Prior art keywords
- scan
- cell
- output
- cells
- real time
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Semiconductor Integrated Circuits (AREA)
- Investigating Or Analysing Biological Materials (AREA)
Abstract
스캔 셀 디자인은 셀의 데이터 입력(DI)이 셀의 스캔 메모리(MI)를 바이패스시키는 접속에 의해 셀의 스캔 출력(SO)에 직접 접속되는 바이패스 모드를 포함한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명에 따른 예시적 내부 스캔 디자인들의 도면.
Claims (2)
- 스캔 셀에 있어서; 스캔 입력; 데이터 입력; 스캔 출력; 상기 스캔 출력과 상기 스캔 및 데이터 입력들과의 사이에 접속된 메모리 회로; 및 상기 스캔 입력을 상기 스캔 출력에 직접 접속시키기 위해 상기 메모리 회로를 바이패싱시키는 회로를 포함하는 것을 특징으로 하는 스캔 셀.
- 다수의 직력-접속된 스캔 셀들을 동작시키는 방법에 있어서; 상기 스캔 셀들 중에 하나를 관측 모드로 배치시키되, 평가될 타켓 회로에 접속되는 데이터 노드 또한 상기 하나의 스캔 셀의 스캔 출력에 직접 접속되는 단계; 및 상기 하나의 스캔 셀이 상기 관측 모드에 있는 동안에, 상기 스캔 셀들 중에 다른 하나를 바이패스 모드로 배치시키되, 그 스캔 출력이 스캔 입력에 직접 접속되는 단계를 포함하는 것을 특징으로 하는 다수의 직력-접속 스캔 셀 동작 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US62965496A | 1996-04-09 | 1996-04-09 | |
US08/629,654 | 1996-04-09 | ||
US08/643,444 US5710779A (en) | 1996-04-09 | 1996-05-08 | Real time data observation method and apparatus |
US08/643,444 | 1996-08-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970071019A true KR970071019A (ko) | 1997-11-07 |
KR100469875B1 KR100469875B1 (ko) | 2005-05-13 |
Family
ID=27090998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970012998A KR100469875B1 (ko) | 1996-04-09 | 1997-04-09 | 실시간데이터관측방법및장치 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5710779A (ko) |
EP (1) | EP0822497B1 (ko) |
KR (1) | KR100469875B1 (ko) |
DE (1) | DE69719416T2 (ko) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6260165B1 (en) | 1996-10-18 | 2001-07-10 | Texas Instruments Incorporated | Accelerating scan test by re-using response data as stimulus data |
US5958076A (en) * | 1996-10-29 | 1999-09-28 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit |
US5909453A (en) * | 1997-07-02 | 1999-06-01 | Xilinx, Inc. | Lookahead structure for fast scan testing |
US6408413B1 (en) | 1998-02-18 | 2002-06-18 | Texas Instruments Incorporated | Hierarchical access of test access ports in embedded core integrated circuits |
US6405335B1 (en) | 1998-02-25 | 2002-06-11 | Texas Instruments Incorporated | Position independent testing of circuits |
US6560734B1 (en) | 1998-06-19 | 2003-05-06 | Texas Instruments Incorporated | IC with addressable test port |
US6694467B2 (en) * | 1999-06-24 | 2004-02-17 | Texas Instruments Incorporated | Low power testing of very large circuits |
US6519729B1 (en) | 1998-06-27 | 2003-02-11 | Texas Instruments Incorporated | Reduced power testing with equally divided scan paths |
US6266801B1 (en) * | 1998-09-15 | 2001-07-24 | Adaptec, Inc. | Boundary-scan cells with improved timing characteristics |
JP2000214220A (ja) | 1999-01-19 | 2000-08-04 | Texas Instr Inc <Ti> | オンチップモジュ―ルおよびオンチップモジュ―ル間の相互接続をテストするシステムおよび方法 |
JP2000275303A (ja) * | 1999-03-23 | 2000-10-06 | Mitsubishi Electric Corp | バウンダリスキャンテスト方法及びバウンダリスキャンテスト装置 |
US7058862B2 (en) * | 2000-05-26 | 2006-06-06 | Texas Instruments Incorporated | Selecting different 1149.1 TAP domains from update-IR state |
GB9920077D0 (en) | 1999-08-24 | 1999-10-27 | Sgs Thomson Microelectronics | Scan latch circuit |
US6272657B1 (en) * | 1999-10-19 | 2001-08-07 | Atmel Corporation | Apparatus and method for progammable parametric toggle testing of digital CMOS pads |
US6728915B2 (en) | 2000-01-10 | 2004-04-27 | Texas Instruments Incorporated | IC with shared scan cells selectively connected in scan path |
US6769080B2 (en) | 2000-03-09 | 2004-07-27 | Texas Instruments Incorporated | Scan circuit low power adapter with counter |
DE60107531T2 (de) * | 2001-02-19 | 2005-12-08 | Lucent Technologies Inc. | Abtastverzögerungskette zur Verzögerungsmessung |
EP1286170A1 (en) * | 2001-08-14 | 2003-02-26 | Lucent Technologies Inc. | Scan flip-flop with bypass of the memory cell of the flipflop |
JP4684942B2 (ja) * | 2006-05-10 | 2011-05-18 | ルネサスエレクトロニクス株式会社 | 半導体装置及び観測用フリップフロップの配置方法 |
US9791505B1 (en) * | 2016-04-29 | 2017-10-17 | Texas Instruments Incorporated | Full pad coverage boundary scan |
EP4180825A1 (en) * | 2021-11-12 | 2023-05-17 | Samsung Electronics Co., Ltd. | Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same |
US11959965B2 (en) | 2021-11-12 | 2024-04-16 | Samsung Electronics Co., Ltd. | Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4872169A (en) * | 1987-03-06 | 1989-10-03 | Texas Instruments Incorporated | Hierarchical scan selection |
JP2676169B2 (ja) * | 1989-12-27 | 1997-11-12 | 三菱電機株式会社 | スキャンパス回路 |
JPH03252569A (ja) * | 1990-02-26 | 1991-11-11 | Advanced Micro Devicds Inc | スキャンパス用レジスタ回路 |
JP2770617B2 (ja) * | 1991-09-05 | 1998-07-02 | 日本電気株式会社 | テスト回路 |
US5528610A (en) * | 1992-04-30 | 1996-06-18 | Hughes Aircraft Company | Boundary test cell with self masking capability |
JP2550837B2 (ja) * | 1992-09-25 | 1996-11-06 | 日本電気株式会社 | スキャンパスのテスト制御回路 |
US5477545A (en) * | 1993-02-09 | 1995-12-19 | Lsi Logic Corporation | Method and apparatus for testing of core-cell based integrated circuits |
US5513186A (en) * | 1993-12-07 | 1996-04-30 | Sun Microsystems, Inc. | Method and apparatus for interconnect testing without speed degradation |
US5550843A (en) * | 1994-04-01 | 1996-08-27 | Xilinx, Inc. | Programmable scan chain testing structure and method |
US5623502A (en) * | 1994-07-15 | 1997-04-22 | National Semiconductor Corporation | Testing of electronic circuits which typically contain asynchronous digital circuitry |
US5570375A (en) * | 1995-05-10 | 1996-10-29 | National Science Council Of R.O.C. | IEEE Std. 1149.1 boundary scan circuit capable of built-in self-testing |
-
1996
- 1996-05-08 US US08/643,444 patent/US5710779A/en not_active Expired - Lifetime
-
1997
- 1997-04-08 EP EP97105801A patent/EP0822497B1/en not_active Expired - Lifetime
- 1997-04-08 DE DE69719416T patent/DE69719416T2/de not_active Expired - Fee Related
- 1997-04-09 KR KR1019970012998A patent/KR100469875B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0822497A2 (en) | 1998-02-04 |
DE69719416T2 (de) | 2004-01-08 |
EP0822497B1 (en) | 2003-03-05 |
KR100469875B1 (ko) | 2005-05-13 |
US5710779A (en) | 1998-01-20 |
DE69719416D1 (de) | 2003-04-10 |
EP0822497A3 (en) | 1998-05-06 |
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