DE69719416D1 - Abtastpfadzelle - Google Patents

Abtastpfadzelle

Info

Publication number
DE69719416D1
DE69719416D1 DE69719416T DE69719416T DE69719416D1 DE 69719416 D1 DE69719416 D1 DE 69719416D1 DE 69719416 T DE69719416 T DE 69719416T DE 69719416 T DE69719416 T DE 69719416T DE 69719416 D1 DE69719416 D1 DE 69719416D1
Authority
DE
Germany
Prior art keywords
cell
scan
abtastpfadzelle
bypasses
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69719416T
Other languages
English (en)
Other versions
DE69719416T2 (de
Inventor
Lee Whetsel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69719416D1 publication Critical patent/DE69719416D1/de
Publication of DE69719416T2 publication Critical patent/DE69719416T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69719416T 1996-04-09 1997-04-08 Abtastpfadzelle Expired - Fee Related DE69719416T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US62965496A 1996-04-09 1996-04-09
US629654 1996-04-09
US08/643,444 US5710779A (en) 1996-04-09 1996-05-08 Real time data observation method and apparatus
US643444 1996-05-08

Publications (2)

Publication Number Publication Date
DE69719416D1 true DE69719416D1 (de) 2003-04-10
DE69719416T2 DE69719416T2 (de) 2004-01-08

Family

ID=27090998

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69719416T Expired - Fee Related DE69719416T2 (de) 1996-04-09 1997-04-08 Abtastpfadzelle

Country Status (4)

Country Link
US (1) US5710779A (de)
EP (1) EP0822497B1 (de)
KR (1) KR100469875B1 (de)
DE (1) DE69719416T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260165B1 (en) 1996-10-18 2001-07-10 Texas Instruments Incorporated Accelerating scan test by re-using response data as stimulus data
US5958076A (en) * 1996-10-29 1999-09-28 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit
US5909453A (en) * 1997-07-02 1999-06-01 Xilinx, Inc. Lookahead structure for fast scan testing
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6560734B1 (en) 1998-06-19 2003-05-06 Texas Instruments Incorporated IC with addressable test port
US6694467B2 (en) * 1999-06-24 2004-02-17 Texas Instruments Incorporated Low power testing of very large circuits
US6519729B1 (en) 1998-06-27 2003-02-11 Texas Instruments Incorporated Reduced power testing with equally divided scan paths
US6266801B1 (en) * 1998-09-15 2001-07-24 Adaptec, Inc. Boundary-scan cells with improved timing characteristics
JP2000214220A (ja) 1999-01-19 2000-08-04 Texas Instr Inc <Ti> オンチップモジュ―ルおよびオンチップモジュ―ル間の相互接続をテストするシステムおよび方法
JP2000275303A (ja) * 1999-03-23 2000-10-06 Mitsubishi Electric Corp バウンダリスキャンテスト方法及びバウンダリスキャンテスト装置
US7058862B2 (en) * 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
GB9920077D0 (en) 1999-08-24 1999-10-27 Sgs Thomson Microelectronics Scan latch circuit
US6272657B1 (en) * 1999-10-19 2001-08-07 Atmel Corporation Apparatus and method for progammable parametric toggle testing of digital CMOS pads
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
EP1233276B1 (de) * 2001-02-19 2004-12-01 Lucent Technologies Inc. Abtastverzögerungskette zur Verzögerungsmessung
EP1286170A1 (de) * 2001-08-14 2003-02-26 Lucent Technologies Inc. Flipflop für "Boundary-Scan" mit Bypass für die Speicherzelle des Flipflops
JP4684942B2 (ja) * 2006-05-10 2011-05-18 ルネサスエレクトロニクス株式会社 半導体装置及び観測用フリップフロップの配置方法
US9791505B1 (en) * 2016-04-29 2017-10-17 Texas Instruments Incorporated Full pad coverage boundary scan
US11959965B2 (en) 2021-11-12 2024-04-16 Samsung Electronics Co., Ltd. Test circuit using clock gating scheme to hold capture procedure and bypass mode, and integrated circuit including the same
EP4180825A1 (de) * 2021-11-12 2023-05-17 Samsung Electronics Co., Ltd. Testschaltung, die ein clock-gating-schema verwendet, um die capture-prozedur und den bypass-modus zu halten, und integrierte schaltung, die diese enthält

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4872169A (en) * 1987-03-06 1989-10-03 Texas Instruments Incorporated Hierarchical scan selection
JP2676169B2 (ja) * 1989-12-27 1997-11-12 三菱電機株式会社 スキャンパス回路
JPH03252569A (ja) * 1990-02-26 1991-11-11 Advanced Micro Devicds Inc スキャンパス用レジスタ回路
JP2770617B2 (ja) * 1991-09-05 1998-07-02 日本電気株式会社 テスト回路
US5528610A (en) * 1992-04-30 1996-06-18 Hughes Aircraft Company Boundary test cell with self masking capability
JP2550837B2 (ja) * 1992-09-25 1996-11-06 日本電気株式会社 スキャンパスのテスト制御回路
US5477545A (en) * 1993-02-09 1995-12-19 Lsi Logic Corporation Method and apparatus for testing of core-cell based integrated circuits
US5513186A (en) * 1993-12-07 1996-04-30 Sun Microsystems, Inc. Method and apparatus for interconnect testing without speed degradation
US5550843A (en) * 1994-04-01 1996-08-27 Xilinx, Inc. Programmable scan chain testing structure and method
US5623502A (en) * 1994-07-15 1997-04-22 National Semiconductor Corporation Testing of electronic circuits which typically contain asynchronous digital circuitry
US5570375A (en) * 1995-05-10 1996-10-29 National Science Council Of R.O.C. IEEE Std. 1149.1 boundary scan circuit capable of built-in self-testing

Also Published As

Publication number Publication date
KR100469875B1 (ko) 2005-05-13
EP0822497A2 (de) 1998-02-04
EP0822497A3 (de) 1998-05-06
DE69719416T2 (de) 2004-01-08
KR970071019A (ko) 1997-11-07
EP0822497B1 (de) 2003-03-05
US5710779A (en) 1998-01-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee