KR970018021A - 반도체물질 박막의 제조방법 - Google Patents
반도체물질 박막의 제조방법 Download PDFInfo
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- KR970018021A KR970018021A KR1019960038442A KR19960038442A KR970018021A KR 970018021 A KR970018021 A KR 970018021A KR 1019960038442 A KR1019960038442 A KR 1019960038442A KR 19960038442 A KR19960038442 A KR 19960038442A KR 970018021 A KR970018021 A KR 970018021A
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- Prior art keywords
- wafer
- layer
- thin film
- stiffening layer
- microblister
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- 239000010409 thin film Substances 0.000 title claims abstract description 8
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 239000000463 material Substances 0.000 title claims description 5
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 238000000926 separation method Methods 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims abstract 12
- 239000002344 surface layer Substances 0.000 claims abstract 5
- 238000010438 heat treatment Methods 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 229910003460 diamond Inorganic materials 0.000 claims 1
- 239000010432 diamond Substances 0.000 claims 1
- 230000004992 fission Effects 0.000 claims 1
- 230000035515 penetration Effects 0.000 claims 1
- 230000008707 rearrangement Effects 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000001179 sorption measurement Methods 0.000 claims 1
- 239000012808 vapor phase Substances 0.000 claims 1
- 238000003776 cleavage reaction Methods 0.000 abstract 1
- 230000007017 scission Effects 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Physical Vapour Deposition (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
Abstract
본 발명은 다음의 단계들을 포함하는 바 : 반도체 웨이퍼(10)내에 이온을 주입(12)하여 상기 웨이퍼 내에 가스상 마이크로블리스터(16)의 분열층을 만들고, 마이크로블리스터층을 따라 표면층(18)이 웨이퍼의 나머지 부분으로부터의 분리가 일어나도록 상기 웨이퍼를 열처리하는 단계를 포함한다.
본 발명에 따르면 상기 주입이 주어진 최소깊이와 같거나 그 이상으로 수행되어 얻어진 박막이 단단하고 상기 열처리가 박막을 방출할 수 있도록 한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 방법의 제1단계에 따라 반도체물질로 이루어진 웨이퍼 내에 이온주입을 하는 것을 개략적으로 보인 것이다,
제2도는 본 발명의 제2단계에 따라 웨이퍼 상부층의 분리에 의하여 박막이 형성되어지는 것을 개략적으로 보인 것이다,
제3도는 본 발명의 개선된 실행에 따라 웨이퍼에 이온을 주입하는 단계를 보인 것이다,
제4도는 본 발명의 개선된 실행에 따른 웨이퍼의 다층박막의 분리를 보인 것이다.
Claims (8)
- 반도체의 결정학적 평면에 거의 평행한, 반도체물질로 이루어진 웨이퍼(10) 표면(14)을 통하여 이온들을 주입하여(12), 웨이퍼(10)내에 표면층(18)의 범위를 정하는, 기체 마이크로블리스터(16)로 이루어진 분열층을 웨이퍼 내에 만들고, 웨이퍼를 충분히 높은 온도에서 열처리하여, 결정재배열효과와 기체 마이크로블리스터(16)내의 압력효과에 기인하여 마이크로블리스터층을 따라 표면층(18)의 웨이퍼 나머지 부분으로부터의 분리가 일어나도록 하되, 이온침투 깊이가, 상기 표면층을 포함하고 충분히 단단하여 상기 열처리에 의하여 방출되어질 수 있는 박막을 얻기 위한 일정한 최소깊이를 초과하는 것을 특징으로 하는 반도체물질로 이루어진 박막제조방법.
- 제1항에 있어서, 웨이퍼(10) 물질의 강도를 초과하는 강도를 가지는 물질로 만들어진 적어도 하나의 이른바 스티프닝층(22)이 상기 이온주입단계 전에 상기 표면(14)위에 형성되어지되, 상기 층의 두께와 주입에너지는 이온들이 상기 스티프닝층을 통과하도록 되어지고, 상기 표면층 및 상기 스티프닝층이 그 다음에 박막을 형성하는 것을 특징으로 하는 반도체물질로 이루어진 박막제조방법.
- 제2항에 있어서, 상기 스티프닝층을 형성하는데에 원자번호 Z인 물질이 사용되어지되, Z≤14인 것을 특징으로 하는 반도체물질로 이루어진 박막제조방법.
- 제2항에 있어서, 상기 스티프닝층이 인핸스드 기상화학증착기술을 사용하여 형성되어지는 것을 특징으로 하는 반도체물질로 이루어진 박막제조방법.
- 제2항에 있어서, 상기 스트프닝층(22)이 흡착에 의하여 웨이퍼(10)의 상기 표면(14)에 부착되어지는 것을 특징으로 하는 반도체물질로 이루어진 박막제조방법.
- 제2항에 있어서, 1μm의 오더(order)의 두께를 가지는 다이아몬드 스티프닝층이 형성되고, 이온주입이 E≥200keV인 에너지 E로 수행되어지는 것을 특징으로 하는 반도체물질로 이루어진 박막제조방법.
- 제2항에 있어서, 실리콘 카바이드 스티프닝층이 1.25μm의 오더의 두께로 형성되고, 이온주입이 E≥200keV인 에너지 E로 수행되어지는 것을 특징으로 하는 반도체물질로 이루어진 박막제조방법.
- 제1항에 있어서, 상기 웨이퍼는 실리콘 또는 실리콘 카바이드이고, 최소깊이는 각각 5μm 및 1.15μm인 것을 특징으로 하는 반도체물질로 이루어진 박막제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US523,581 | 1995-09-05 | ||
JP95-257162 | 1995-09-08 | ||
FR9510718A FR2738671B1 (fr) | 1995-09-13 | 1995-09-13 | Procede de fabrication de films minces a materiau semiconducteur |
FR9510718 | 1995-09-13 | ||
JP95-264833 | 1995-09-19 | ||
US08/530,612 | 1995-09-20 | ||
JP95-245636 | 1995-09-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970018021A true KR970018021A (ko) | 1997-04-30 |
KR100400684B1 KR100400684B1 (ko) | 2004-01-14 |
Family
ID=9482495
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960038442A KR100400684B1 (ko) | 1995-09-13 | 1996-09-05 | 반도체물질 박막의 제조방법 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5714395A (ko) |
EP (1) | EP0763849B1 (ko) |
JP (1) | JP4049834B2 (ko) |
KR (1) | KR100400684B1 (ko) |
DE (1) | DE69617147T2 (ko) |
FR (1) | FR2738671B1 (ko) |
Cited By (1)
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KR100797851B1 (ko) * | 2001-12-19 | 2008-01-24 | 주식회사 포스코 | 시편 인출장치 |
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FR2506344B2 (fr) * | 1980-02-01 | 1986-07-11 | Commissariat Energie Atomique | Procede de dopage de semi-conducteurs |
FR2475068B1 (fr) * | 1980-02-01 | 1986-05-16 | Commissariat Energie Atomique | Procede de dopage de semi-conducteurs |
FR2650704B1 (fr) * | 1989-08-01 | 1994-05-06 | Thomson Csf | Procede de fabrication par epitaxie de couches monocristallines de materiaux a parametres de mailles differents |
GB2237143A (en) * | 1989-09-15 | 1991-04-24 | Philips Electronic Associated | Two-terminal non-linear devices and their fabrication |
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US5198371A (en) * | 1990-09-24 | 1993-03-30 | Biota Corp. | Method of making silicon material with enhanced surface mobility by hydrogen ion implantation |
JPH04365377A (ja) * | 1991-06-13 | 1992-12-17 | Agency Of Ind Science & Technol | 半導体装置 |
FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
FR2714524B1 (fr) * | 1993-12-23 | 1996-01-26 | Commissariat Energie Atomique | Procede de realisation d'une structure en relief sur un support en materiau semiconducteur |
FR2715501B1 (fr) * | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Procédé de dépôt de lames semiconductrices sur un support. |
-
1995
- 1995-09-13 FR FR9510718A patent/FR2738671B1/fr not_active Expired - Lifetime
-
1996
- 1996-09-03 JP JP23342896A patent/JP4049834B2/ja not_active Expired - Lifetime
- 1996-09-05 KR KR1019960038442A patent/KR100400684B1/ko not_active IP Right Cessation
- 1996-09-10 DE DE69617147T patent/DE69617147T2/de not_active Expired - Lifetime
- 1996-09-10 EP EP96401932A patent/EP0763849B1/fr not_active Expired - Lifetime
- 1996-09-12 US US08/713,201 patent/US5714395A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100797851B1 (ko) * | 2001-12-19 | 2008-01-24 | 주식회사 포스코 | 시편 인출장치 |
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US5714395A (en) | 1998-02-03 |
JPH09181011A (ja) | 1997-07-11 |
KR100400684B1 (ko) | 2004-01-14 |
DE69617147T2 (de) | 2002-07-04 |
EP0763849B1 (fr) | 2001-11-21 |
FR2738671B1 (fr) | 1997-10-10 |
DE69617147D1 (de) | 2002-01-03 |
JP4049834B2 (ja) | 2008-02-20 |
EP0763849A1 (fr) | 1997-03-19 |
FR2738671A1 (fr) | 1997-03-14 |
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