KR970008810B1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR970008810B1
KR970008810B1 KR93005638A KR930005638A KR970008810B1 KR 970008810 B1 KR970008810 B1 KR 970008810B1 KR 93005638 A KR93005638 A KR 93005638A KR 930005638 A KR930005638 A KR 930005638A KR 970008810 B1 KR970008810 B1 KR 970008810B1
Authority
KR
South Korea
Prior art keywords
potential supply
power potential
chip area
voltage stress
semiconductor device
Prior art date
Application number
KR93005638A
Other languages
English (en)
Other versions
KR930022511A (ko
Inventor
Hiroshi Sahara
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of KR930022511A publication Critical patent/KR930022511A/ko
Application granted granted Critical
Publication of KR970008810B1 publication Critical patent/KR970008810B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
KR93005638A 1992-04-08 1993-04-03 Semiconductor device KR970008810B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-086962 1992-04-08
JP4086962A JP2793427B2 (ja) 1992-04-08 1992-04-08 半導体装置

Publications (2)

Publication Number Publication Date
KR930022511A KR930022511A (ko) 1993-11-24
KR970008810B1 true KR970008810B1 (en) 1997-05-29

Family

ID=13901502

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93005638A KR970008810B1 (en) 1992-04-08 1993-04-03 Semiconductor device

Country Status (5)

Country Link
US (1) US5404099A (ko)
EP (1) EP0565079B1 (ko)
JP (1) JP2793427B2 (ko)
KR (1) KR970008810B1 (ko)
DE (1) DE69326710T2 (ko)

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KR0122100B1 (ko) * 1994-03-10 1997-11-26 김광호 스트레스회로를 가지는 반도체집적회로 및 그 스트레스전압공급방법
US5623202A (en) * 1994-09-26 1997-04-22 United Microelectronics Corporation Testing multiple IC in parallel by a single IC tester
JP3301874B2 (ja) * 1994-12-19 2002-07-15 松下電器産業株式会社 半導体装置及びその検査方法
JP3130769B2 (ja) * 1995-09-28 2001-01-31 山口日本電気株式会社 半導体装置
US5721495A (en) * 1995-10-24 1998-02-24 Unisys Corporation Circuit for measuring quiescent current
US5652524A (en) * 1995-10-24 1997-07-29 Unisys Corporation Built-in load board design for performing high resolution quiescent current measurements of a device under test
JP4041156B2 (ja) * 1996-05-30 2008-01-30 株式会社東芝 半導体集積回路装置の検査方法
US5898706A (en) * 1997-04-30 1999-04-27 International Business Machines Corporation Structure and method for reliability stressing of dielectrics
JP3660783B2 (ja) * 1997-06-30 2005-06-15 松下電器産業株式会社 半導体集積回路
KR100515025B1 (ko) * 1997-11-15 2005-12-01 삼성전자주식회사 테스트/접지 겸용 핀을 구비하는 반도체 장치
KR100269322B1 (ko) * 1998-01-16 2000-10-16 윤종용 스트레스용전압을이용하여메모리를테스팅하는기능을갖는집적회로및그의메모리테스트방법
US6456099B1 (en) * 1998-12-31 2002-09-24 Formfactor, Inc. Special contact points for accessing internal circuitry of an integrated circuit
US6499121B1 (en) 1999-03-01 2002-12-24 Formfactor, Inc. Distributed interface for parallel testing of multiple devices using a single tester channel
US6480978B1 (en) 1999-03-01 2002-11-12 Formfactor, Inc. Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons
KR100372661B1 (ko) * 1999-06-30 2003-02-17 주식회사 하이닉스반도체 직류 스트레스 인가 회로 및 이를 이용한 반도체 회로
JP4266254B2 (ja) 1999-07-19 2009-05-20 株式会社ルネサステクノロジ 半導体記憶装置
US7173444B2 (en) 2000-04-04 2007-02-06 Ali Pourkeramati Structure and method for parallel testing of dies on a semiconductor wafer
US6323639B1 (en) 2000-04-04 2001-11-27 Azalea Microelectronics Corporation Powering dies on a semiconductor wafer through wafer scribe line areas
US6617862B1 (en) * 2002-02-27 2003-09-09 Advanced Micro Devices, Inc. Laser intrusive technique for locating specific integrated circuit current paths
JP4516294B2 (ja) 2003-09-30 2010-08-04 パナソニック株式会社 半導体装置及び半導体装置の製造方法
US7228457B2 (en) * 2004-03-16 2007-06-05 Arm Limited Performing diagnostic operations upon a data processing apparatus with power down support
US8035188B2 (en) 2004-07-28 2011-10-11 Panasonic Corporation Semiconductor device
KR100630714B1 (ko) * 2004-11-10 2006-10-04 삼성전자주식회사 트위스트 비트 라인들에 센싱 스트레스를 효과적으로 줄수 있는 프리차아지부를 갖는 메모리 장치, 그 웨이퍼번-인 테스트 방법 및 프리차아지부의 배치 방법
JP4623659B2 (ja) 2006-02-23 2011-02-02 パナソニック株式会社 半導体装置
JP4851216B2 (ja) * 2006-03-28 2012-01-11 富士通セミコンダクター株式会社 半導体集積回路における試験時の電源供給方法および半導体集積回路用ｃａｄシステム
WO2007138711A1 (ja) 2006-06-01 2007-12-06 Fujitsu Limited 多電源集積回路を有する電子機器システム
JP2008306035A (ja) * 2007-06-08 2008-12-18 Seiko Epson Corp 半導体装置及びその検査方法
JP2009130310A (ja) * 2007-11-28 2009-06-11 Elpida Memory Inc 半導体集積回路
TWI362902B (en) 2008-09-02 2012-04-21 E Ink Holdings Inc Bistable display device
KR20100125099A (ko) * 2009-05-20 2010-11-30 삼성전자주식회사 반도체 장치
US8436635B2 (en) * 2009-09-01 2013-05-07 Texas Instruments Incorporated Semiconductor wafer having test modules including pin matrix selectable test devices
TWI413777B (zh) * 2010-09-01 2013-11-01 Multi - power circuit board and its application probe card
US8823405B1 (en) * 2010-09-10 2014-09-02 Xilinx, Inc. Integrated circuit with power gating
DE112014002086T5 (de) * 2013-04-22 2016-01-14 Ignis Innovation Inc. Prüfsystem für OLED-Anzeigebildschirme
US20140354325A1 (en) * 2013-05-28 2014-12-04 United Microelectronics Corp. Semiconductor layout structure and testing method thereof
WO2021095232A1 (ja) * 2019-11-15 2021-05-20 キオクシア株式会社 ストレージシステム及びウェハ
JP2023015658A (ja) 2021-07-20 2023-02-01 株式会社東芝 多チャネルスイッチｉｃ

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US4393475A (en) * 1981-01-27 1983-07-12 Texas Instruments Incorporated Non-volatile semiconductor memory and the testing method for the same
JPS62114200A (ja) * 1985-11-13 1987-05-25 Mitsubishi Electric Corp 半導体メモリ装置
KR900004989B1 (en) * 1986-09-11 1990-07-16 Fujitsu Ltd Active matrix type display and driving method
US4970454A (en) * 1986-12-09 1990-11-13 Texas Instruments Incorporated Packaged semiconductor device with test circuits for determining fabrication parameters
JP2827229B2 (ja) * 1988-10-14 1998-11-25 日本電気株式会社 半導体集積回路
JP2558881B2 (ja) * 1989-06-30 1996-11-27 株式会社東芝 半導体メモリ装置
US5097206A (en) * 1990-10-05 1992-03-17 Hewlett-Packard Company Built-in test circuit for static CMOS circuits
JP2647546B2 (ja) * 1990-10-11 1997-08-27 シャープ株式会社 半導体記憶装置のテスト方法
JP3237127B2 (ja) * 1991-04-19 2001-12-10 日本電気株式会社 ダイナミックランダムアクセスメモリ装置

Also Published As

Publication number Publication date
DE69326710T2 (de) 2000-03-09
JPH05291368A (ja) 1993-11-05
JP2793427B2 (ja) 1998-09-03
EP0565079B1 (en) 1999-10-13
DE69326710D1 (de) 1999-11-18
US5404099A (en) 1995-04-04
EP0565079A1 (en) 1993-10-13
KR930022511A (ko) 1993-11-24

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E902 Notification of reason for refusal
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