KR960030328A - 반도체 장치의 금속층 형성방법 - Google Patents
반도체 장치의 금속층 형성방법 Download PDFInfo
- Publication number
- KR960030328A KR960030328A KR1019950000133A KR19950000133A KR960030328A KR 960030328 A KR960030328 A KR 960030328A KR 1019950000133 A KR1019950000133 A KR 1019950000133A KR 19950000133 A KR19950000133 A KR 19950000133A KR 960030328 A KR960030328 A KR 960030328A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive film
- forming
- semiconductor device
- metal layer
- melting point
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000002184 metal Substances 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 title claims abstract 11
- 230000015572 biosynthetic process Effects 0.000 title claims 2
- 239000012535 impurity Substances 0.000 claims abstract 8
- 230000008018 melting Effects 0.000 claims abstract 8
- 238000002844 melting Methods 0.000 claims abstract 8
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract 6
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract 4
- 150000002500 ions Chemical class 0.000 claims abstract 4
- 229910052802 copper Inorganic materials 0.000 claims abstract 3
- 229910052763 palladium Inorganic materials 0.000 claims abstract 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract 3
- 229910052718 tin Inorganic materials 0.000 claims abstract 3
- 229910052720 vanadium Inorganic materials 0.000 claims abstract 3
- 238000004544 sputter deposition Methods 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims abstract 2
- 229910052733 gallium Inorganic materials 0.000 claims 2
- 229910052732 germanium Inorganic materials 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체 장치의 금속층 형성방법으로서, 기판위에 제1전도성막을 형성하는 공정과, 제1전도성막보다 저융점의 제2전도성막을 제1전도성막위에 형성하는 공정과, 제2전도성막을 용융시키는 공정을 포함하여 이루어진다.
제1전도성막은 화학기상증착법으로 형성하고, 제2전도성막은 제1전도성막에 불순물이온을 주입하여 형성하거나, 제1전도성막위에 제2전도성막을 화학기상증착방법으로 형성하면 된다. 화학기상증착방법은 스퍼터링 방법도 포함한다.
또 제1전도성막은 A1 또는 Al 합금을 이용하고, 불순물로서는 Si, Cu, Ga, Gc, Pd, Sn, V등을 이용하면되며, 제2전도성막이 제1전도성막보다 10℃ 이상 낮은 융점을 갖도록 한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 A, B, C는 본 발명의 금속층 형성방법의 일실시예를 설명하기 위한 공정 단계별 콘택부위의 일부 단면도이다.
Claims (11)
- 반도체 장치의 금속층 형성방법에 있어서, 기판위에 제1전도성막을 형성하는 공정과, 제1전도성막 보다저융점의 제2전도성막을 제1전도성막위에 형성하는 공정과, 제2전도성막 만을 용융시키는 공정을 포함하여 이루어지는 반도체 장치의 금속층 형성방법.
- 제1항에 있어서, 제1전도성막을 형성하는 공정은 화학기상증착법을 적용하는 것이 특징인 반도체 장치의 금속층 형성방법.
- 제1항에 있어서, 제1전도성막은 Al 또는 Al 합금으로 형성된 것이 특징인 반도체 장치의 금속층 형성방법.
- 제1항에 있어서, 제2전도성막을 형성하는 공정은 제1전도성막에 불순물이온을 주입하는 공정을 포함하는 것이 특징인 반도체 장치의 금속층 형성방법.
- 제4항에 있어서, 제1전도성막은 Al 또는 Al 합금으로 형성된 것이고, 상기 불순물이온으로서는 Si, Cu, Ga, Ge, Pd, Sn, V, 등에서 하나이상 선택하여 사용하는 것이 특징인 반도체 장치의 금속층 형성방법.
- 제4항에 있어서, 불순물이온의 농도는 저융점의 도전층이 전도성막보다 10℃ 이상 낮은 융점을 갖도록 하는 조성인 것이 특징인 반도체 장치의 금속층 형성방법.
- 제1항에 있어서, 제2전도성막을 형성하는 공정은 제1전도성막위에 제2전도성막을 화학기상증착방법으로 형성하는 것이 특징인 반도체 장치의 금속층 형성방법.
- 제7항에 있어서, 제1전도성막은 Al 또는 Al 합금으로 형성하고, 제2전도성막은 제1전도성막 보다 불순물이 많이 포함된 증착막으로 형성하는 것이 특징인 반도체 장치의 금속층 형성방법.
- 제8항에 있어서, 불순물로서는 Si, Cu, Ga, Ge, Pd, Sn, V등을 하나이상 선택하여 사용하는 것이 특징인 반도체 장치의 금속층 형성방법.
- 제8항에 있어서, 불순물 농도는 제2전도성막이 제1전도성막보다 10℃ 이상 낮은 융점을 갖는 조성인 것을 포함하는 것이 특징인 반도체 장치의 금속층 형성방법.
- 제7항에 있어서, 화학기상 증착막을 형성하는 공정으로서는 스퍼터링방식을 적용하는 것이 특징인 반도체 장치의 금속층 형성방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950000133A KR0161116B1 (ko) | 1995-01-06 | 1995-01-06 | 반도체 장치의 금속층 형성방법 |
JP07231356A JP3113800B2 (ja) | 1995-01-06 | 1995-09-08 | 半導体装置の配線形成方法 |
US08/583,320 US5880023A (en) | 1995-01-06 | 1996-01-05 | Process for formation of wiring layer in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950000133A KR0161116B1 (ko) | 1995-01-06 | 1995-01-06 | 반도체 장치의 금속층 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960030328A true KR960030328A (ko) | 1996-08-17 |
KR0161116B1 KR0161116B1 (ko) | 1999-02-01 |
Family
ID=19406428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950000133A KR0161116B1 (ko) | 1995-01-06 | 1995-01-06 | 반도체 장치의 금속층 형성방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5880023A (ko) |
JP (1) | JP3113800B2 (ko) |
KR (1) | KR0161116B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004049181A1 (en) * | 2002-11-27 | 2004-06-10 | Il-Sung Park | Method of displaying number as character and electronic calculator using the same |
Families Citing this family (13)
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US6225218B1 (en) * | 1995-12-20 | 2001-05-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and its manufacturing method |
US6268291B1 (en) | 1995-12-29 | 2001-07-31 | International Business Machines Corporation | Method for forming electromigration-resistant structures by doping |
US5789317A (en) | 1996-04-12 | 1998-08-04 | Micron Technology, Inc. | Low temperature reflow method for filling high aspect ratio contacts |
KR100421281B1 (ko) * | 1996-10-02 | 2004-05-10 | 주식회사 하이닉스반도체 | 반도체소자의금속배선제조방법 |
JP3725266B2 (ja) | 1996-11-07 | 2005-12-07 | 株式会社半導体エネルギー研究所 | 配線形成方法 |
US6171957B1 (en) * | 1997-07-16 | 2001-01-09 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing method of semiconductor device having high pressure reflow process |
US6159847A (en) * | 1997-11-18 | 2000-12-12 | Texas Instruments Incorporated | Multilayer metal structure for improved interconnect reliability |
US6605531B1 (en) * | 1997-11-26 | 2003-08-12 | Applied Materials, Inc. | Hole-filling technique using CVD aluminum and PVD aluminum integration |
US7211502B2 (en) * | 2003-03-26 | 2007-05-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
JP2005340424A (ja) * | 2004-05-26 | 2005-12-08 | Nec Electronics Corp | 半導体装置およびその製造方法 |
KR100595855B1 (ko) * | 2004-12-29 | 2006-06-30 | 동부일렉트로닉스 주식회사 | 알루미늄 증착 콘택트 형성 방법 |
JP5560841B2 (ja) * | 2010-03-30 | 2014-07-30 | 凸版印刷株式会社 | 非接触ic内蔵用紙ならびにic付き冊子またはicカード |
CN110634952B (zh) * | 2018-06-25 | 2023-06-13 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
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US3871067A (en) * | 1973-06-29 | 1975-03-18 | Ibm | Method of manufacturing a semiconductor device |
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US5693564A (en) * | 1994-12-22 | 1997-12-02 | Intel Corporation | Conductor fill reflow with intermetallic compound wetting layer for semiconductor fabrication |
US5789317A (en) * | 1996-04-12 | 1998-08-04 | Micron Technology, Inc. | Low temperature reflow method for filling high aspect ratio contacts |
US5798296A (en) * | 1996-05-17 | 1998-08-25 | Micron Technology, Inc. | Method of fabricating a gate having a barrier of titanium silicide |
-
1995
- 1995-01-06 KR KR1019950000133A patent/KR0161116B1/ko not_active IP Right Cessation
- 1995-09-08 JP JP07231356A patent/JP3113800B2/ja not_active Expired - Fee Related
-
1996
- 1996-01-05 US US08/583,320 patent/US5880023A/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004049181A1 (en) * | 2002-11-27 | 2004-06-10 | Il-Sung Park | Method of displaying number as character and electronic calculator using the same |
Also Published As
Publication number | Publication date |
---|---|
JP3113800B2 (ja) | 2000-12-04 |
KR0161116B1 (ko) | 1999-02-01 |
JPH08204013A (ja) | 1996-08-09 |
US5880023A (en) | 1999-03-09 |
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