KR960030311A - 반도체소자의 제조방법 - Google Patents
반도체소자의 제조방법 Download PDFInfo
- Publication number
- KR960030311A KR960030311A KR1019950000270A KR19950000270A KR960030311A KR 960030311 A KR960030311 A KR 960030311A KR 1019950000270 A KR1019950000270 A KR 1019950000270A KR 19950000270 A KR19950000270 A KR 19950000270A KR 960030311 A KR960030311 A KR 960030311A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- oxide film
- trench
- etching
- region
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract 5
- 239000004065 semiconductor Substances 0.000 title claims abstract 5
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract 7
- 238000005468 ion implantation Methods 0.000 claims abstract 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract 6
- 238000001312 dry etching Methods 0.000 claims abstract 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 3
- 238000005530 etching Methods 0.000 claims abstract 3
- 230000003647 oxidation Effects 0.000 claims abstract 3
- 238000007254 oxidation reaction Methods 0.000 claims abstract 3
- 229910052710 silicon Inorganic materials 0.000 claims abstract 3
- 239000010703 silicon Substances 0.000 claims abstract 3
- 238000001039 wet etching Methods 0.000 claims abstract 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 식각기술을 이용하여 실리콘 기판내에 매몰산화막을 형성하여 SOI구조 형성을 위한 활성영역을 갖춘 기판을 형성하는 방법에 관한 것이다.
본 발명은 단결정 실리콘웨이퍼상에 산화막을 형성하는 공정과, 상기 산화막을 선택적으로 건식식각하여 소자가 형성될 활성영역상에만 남기는 공정, 상기 산화막의 식각에 의해 노출되는 기판부위를 건식식각하여 소정 깊이의 트렌치를 형성하는 공정, 상기 트렌치 하부의 양단부위에 국부적인 이온주입영역을 형성하는 공정, 상기 산화막을 제거하는 공정, 상기 단결정 실리콘웨이퍼를 습식식각하는 공정, 및 산화공정을 행하여 실시하면 상기 트렌치 하부영역에 매몰산화막을 형성하는 공정을 포함하는 반도체소자의 제조방법을 제공한다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 일실시예에 의한 SOI구조 형성방법을 도시한 공정순서도.
Claims (3)
- 단결정 실리콘웨이퍼상에 산화막을 형성하는 공정과, 상기 산화막을 선택적으로 건식식각하여 소자가 형성될 활성영역상에만 남기는 공정, 상기 산화막의 식각에 의해 노출되는 기판부위를 건식식각하여 소정깊이의 트렌치를 형성하는 공정, 상기 트렌치 하부의 양단 주위에 국부적인 이온주입영역을 형성하는 공정, 상기 산화막을 제거하는 공정, 상기 단결정 실리콘웨이퍼를 습식식각하는 공정, 및 산화공정을 행하여 실시하면 상기 트렌치 하부영역에 매몰산화막을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 제조방법.
- 제1항에 있어서, 상기 국부적인 이온주입영역은 상기 산화막을 마스크로 이용하여 상기 단결정 실리콘웨이퍼를 회전시키면서 경사 이온주입을 실시하여 형성하는 것을 특징으로 하는 반도체소자의 제조방법.
- 단결정 실리콘기판내의 소정깊이에 이온주입층을 형성하는 공정과, 상기 실리콘기판의 소자가 형성될 활성영역을 제외한 영역을 상기 이온주입층이 노출될 때까지 선택적으로 건식식각하여 트렌치를 형성하는 공정, 상기 실리콘기판을 습식식각하는 공정, 및 산화공정을 실시하여 상기 트렌치 하부영역에 매몰산화막을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950000270A KR0161852B1 (ko) | 1995-01-09 | 1995-01-09 | 반도체소자의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950000270A KR0161852B1 (ko) | 1995-01-09 | 1995-01-09 | 반도체소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960030311A true KR960030311A (ko) | 1996-08-17 |
KR0161852B1 KR0161852B1 (ko) | 1999-02-01 |
Family
ID=19406539
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950000270A KR0161852B1 (ko) | 1995-01-09 | 1995-01-09 | 반도체소자의 제조방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0161852B1 (ko) |
-
1995
- 1995-01-09 KR KR1019950000270A patent/KR0161852B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0161852B1 (ko) | 1999-02-01 |
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