KR960030311A - 반도체소자의 제조방법 - Google Patents

반도체소자의 제조방법 Download PDF

Info

Publication number
KR960030311A
KR960030311A KR1019950000270A KR19950000270A KR960030311A KR 960030311 A KR960030311 A KR 960030311A KR 1019950000270 A KR1019950000270 A KR 1019950000270A KR 19950000270 A KR19950000270 A KR 19950000270A KR 960030311 A KR960030311 A KR 960030311A
Authority
KR
South Korea
Prior art keywords
forming
oxide film
trench
etching
region
Prior art date
Application number
KR1019950000270A
Other languages
English (en)
Other versions
KR0161852B1 (ko
Inventor
이병주
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019950000270A priority Critical patent/KR0161852B1/ko
Publication of KR960030311A publication Critical patent/KR960030311A/ko
Application granted granted Critical
Publication of KR0161852B1 publication Critical patent/KR0161852B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 식각기술을 이용하여 실리콘 기판내에 매몰산화막을 형성하여 SOI구조 형성을 위한 활성영역을 갖춘 기판을 형성하는 방법에 관한 것이다.
본 발명은 단결정 실리콘웨이퍼상에 산화막을 형성하는 공정과, 상기 산화막을 선택적으로 건식식각하여 소자가 형성될 활성영역상에만 남기는 공정, 상기 산화막의 식각에 의해 노출되는 기판부위를 건식식각하여 소정 깊이의 트렌치를 형성하는 공정, 상기 트렌치 하부의 양단부위에 국부적인 이온주입영역을 형성하는 공정, 상기 산화막을 제거하는 공정, 상기 단결정 실리콘웨이퍼를 습식식각하는 공정, 및 산화공정을 행하여 실시하면 상기 트렌치 하부영역에 매몰산화막을 형성하는 공정을 포함하는 반도체소자의 제조방법을 제공한다.

Description

반도체소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 일실시예에 의한 SOI구조 형성방법을 도시한 공정순서도.

Claims (3)

  1. 단결정 실리콘웨이퍼상에 산화막을 형성하는 공정과, 상기 산화막을 선택적으로 건식식각하여 소자가 형성될 활성영역상에만 남기는 공정, 상기 산화막의 식각에 의해 노출되는 기판부위를 건식식각하여 소정깊이의 트렌치를 형성하는 공정, 상기 트렌치 하부의 양단 주위에 국부적인 이온주입영역을 형성하는 공정, 상기 산화막을 제거하는 공정, 상기 단결정 실리콘웨이퍼를 습식식각하는 공정, 및 산화공정을 행하여 실시하면 상기 트렌치 하부영역에 매몰산화막을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 제조방법.
  2. 제1항에 있어서, 상기 국부적인 이온주입영역은 상기 산화막을 마스크로 이용하여 상기 단결정 실리콘웨이퍼를 회전시키면서 경사 이온주입을 실시하여 형성하는 것을 특징으로 하는 반도체소자의 제조방법.
  3. 단결정 실리콘기판내의 소정깊이에 이온주입층을 형성하는 공정과, 상기 실리콘기판의 소자가 형성될 활성영역을 제외한 영역을 상기 이온주입층이 노출될 때까지 선택적으로 건식식각하여 트렌치를 형성하는 공정, 상기 실리콘기판을 습식식각하는 공정, 및 산화공정을 실시하여 상기 트렌치 하부영역에 매몰산화막을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950000270A 1995-01-09 1995-01-09 반도체소자의 제조방법 KR0161852B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950000270A KR0161852B1 (ko) 1995-01-09 1995-01-09 반도체소자의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950000270A KR0161852B1 (ko) 1995-01-09 1995-01-09 반도체소자의 제조방법

Publications (2)

Publication Number Publication Date
KR960030311A true KR960030311A (ko) 1996-08-17
KR0161852B1 KR0161852B1 (ko) 1999-02-01

Family

ID=19406539

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950000270A KR0161852B1 (ko) 1995-01-09 1995-01-09 반도체소자의 제조방법

Country Status (1)

Country Link
KR (1) KR0161852B1 (ko)

Also Published As

Publication number Publication date
KR0161852B1 (ko) 1999-02-01

Similar Documents

Publication Publication Date Title
KR970030640A (ko) 반도체 장치의 소자 분리막 형성방법
KR920013670A (ko) 반도체 장치의 소자분리방법
KR960042931A (ko) Soi 구조를 갖는 반도체장치의 제조방법
KR980006032A (ko) 반도체 소자의 격리영역 형성방법
KR960030311A (ko) 반도체소자의 제조방법
KR970003791A (ko) 반도체 소자의 소자분리막 형성방법
KR970054268A (ko) 반도체 에스 오 아이 소자의 제조방법
KR960005940A (ko) 소자분리 산화막 형성 방법
KR970054111A (ko) 반도체소자의 제조방법
KR980006074A (ko) 반도체 소자의 필드 산화막 형성방법
KR980006105A (ko) 반도체 메모리 장치 및 그 제조방법
KR970008483A (ko) 반도체장치 제조방법
KR920010917A (ko) 트랜치를 이용한 스택커패시터의 제조방법
KR960019650A (ko) 반도체장치의 격리방법
KR950021362A (ko) 반도체 소자 격리방법
KR880013236A (ko) 반도체 장치의 제조방법
KR970003937A (ko) 금속 산화물 실리콘 전계 효과 트랜지스터의 제조방법
KR970003823A (ko) 반도체 소자의 소자분리막 형성방법
KR960039432A (ko) 반도체소자 및 그 제조방법
KR960026610A (ko) 반도체 소자의 필드산화막 형성방법
KR970018080A (ko) 반도체장치의 콘택형성방법
KR910013511A (ko) 반도체 소자의 소자분리 산화막 형성방법
KR960026729A (ko) 반도체 소자의 소자분리막 형성방법
KR970052189A (ko) 반도체 소자의 필드 산화막 형성방법
KR960026582A (ko) 반도체소자의 소자분리 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090727

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee