KR960026582A - 반도체소자의 소자분리 방법 - Google Patents

반도체소자의 소자분리 방법 Download PDF

Info

Publication number
KR960026582A
KR960026582A KR1019940039012A KR19940039012A KR960026582A KR 960026582 A KR960026582 A KR 960026582A KR 1019940039012 A KR1019940039012 A KR 1019940039012A KR 19940039012 A KR19940039012 A KR 19940039012A KR 960026582 A KR960026582 A KR 960026582A
Authority
KR
South Korea
Prior art keywords
device isolation
oxide film
semiconductor substrate
isolation oxide
trenches
Prior art date
Application number
KR1019940039012A
Other languages
English (en)
Other versions
KR0161727B1 (ko
Inventor
김승준
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940039012A priority Critical patent/KR0161727B1/ko
Publication of KR960026582A publication Critical patent/KR960026582A/ko
Application granted granted Critical
Publication of KR0161727B1 publication Critical patent/KR0161727B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체소자의 소자분리 방법에 관한 것으로서, 반도체기판에서 비교적 폭이 넓은 소자분리영역으로 예정되어 있는 반도체 기판상에 고농도의 불순물 이온주입을 하고, 비교적 폭이 작은 소자분리영역으로 예정되어 있는 부분들에 트랜치를 형성한 후, 반도체기판상에 불순물 이온이 주입된 영역, 즉 폭이 넓은 소자 분리영역에 열산화를 실시하여 불순물 이온이 주입되지 않은 영역에서보다 두꺼운 제1소자분리 산화막을 형성하고, 전표면에 제2소자분리 산화막을 도포하여 상기 트랜치들을 메운 다음 전면 이방성식각을 실시하여 평탄화하는 반도체소자의 소자분리 방법으로, 공정이 간단하며 소자동작의 신뢰성 및 공정수율을 향상시킬 수 있다.

Description

반도체소자의 소자분리 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 제1E도는 본 발명에 따른 반도체소자의 소자분리 공정도.

Claims (6)

  1. 반도체기판에서 예정된 이상의 폭을 갖는 소자분리영역으로 예정되어 있는 부분에 불순물 이온주입을 실시하여 표면을 손상시키는 공정과, 상기 반도체기판에서 예정된 폭 이하의 폭을 갖는 소자분리 영역으로 예정되어 있는 부분들에 트랜치를 형성하는 공정과, 상기 불순물 이온주입 영역의 반도체기판을 열산화시켜 제1소자분리 산화막을 형성하는 공정과, 상기 구조의 전표면에 제2소자분리 산화막을 형성하여 상기 트랜치들을 메우는 공정과, 상기 제2소자분리 산화막을 전면 식각하여 평탄화하는 공정을 구비하는 반도체소자의 소자분리 방법.
  2. 제1항에 있어서, 상기 트랜치들의 폭이 0.1~0.5㎛의 폭을 갖는 것을 특징으로 하는 반도체소자의 소자분리 방법.
  3. 제1항에 있어서, 상기 제1소자분리 산화막의 폭이 0.5~5㎛인 것을 특징으로 하는 반도체소자의 소자분리 방법.
  4. 제1항에 있어서, 상기 이온주입되는 불순물이 Si, P, B 및 As로 이루어지는 군에서 임의로 선택되는 하나의 불순물인 것을 특징으로 하는 반도체소자의 소자분리 방법.
  5. 제1항에 있어서, 상기 불순물 이온주입을 1×10E12㎝-2~1×10E19㎝-2의 범위에서 실시하는 것을 특징으로 하는 반도체소자의 소자분리 방법.
  6. 제1항에 있어서, 상기 제2소자분리 산화막이 CVD 방법으로 형성되는 것을 특징으로 하는 반도체소자의 소자분리 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940039012A 1994-12-29 1994-12-29 반도체 소자의 소자분리방법 KR0161727B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940039012A KR0161727B1 (ko) 1994-12-29 1994-12-29 반도체 소자의 소자분리방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940039012A KR0161727B1 (ko) 1994-12-29 1994-12-29 반도체 소자의 소자분리방법

Publications (2)

Publication Number Publication Date
KR960026582A true KR960026582A (ko) 1996-07-22
KR0161727B1 KR0161727B1 (ko) 1999-02-01

Family

ID=19405214

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940039012A KR0161727B1 (ko) 1994-12-29 1994-12-29 반도체 소자의 소자분리방법

Country Status (1)

Country Link
KR (1) KR0161727B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100342381B1 (ko) * 1998-04-14 2003-07-07 아남반도체 주식회사 반도체소자의절연막형성방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100342381B1 (ko) * 1998-04-14 2003-07-07 아남반도체 주식회사 반도체소자의절연막형성방법

Also Published As

Publication number Publication date
KR0161727B1 (ko) 1999-02-01

Similar Documents

Publication Publication Date Title
KR950021347A (ko) 반도체장치의 제조방법
KR970030640A (ko) 반도체 장치의 소자 분리막 형성방법
KR960019649A (ko) 반도체 장치의 제조방법
KR960026582A (ko) 반도체소자의 소자분리 방법
KR960042931A (ko) Soi 구조를 갖는 반도체장치의 제조방법
EP0239384A3 (en) Process for isolating semiconductor devices on a substrate
KR960026278A (ko) 반도체소자의 소자분리 방법
KR940012575A (ko) 반도체 소자의 트렌치 아이솔레이션 제조 방법
JPS60105247A (ja) 半導体装置の製造方法
KR970053492A (ko) 반도체 소자 분리방법
KR970053376A (ko) 반도체 소자의 소자분리막 형성방법
JPS60126846A (ja) 半導体装置およびその製造方法
KR960026586A (ko) 반도체 소자의 소자분리 방법
KR970053482A (ko) 반도체 소자의 필드 산화막 형성방법
KR960039270A (ko) 반도체소자 격리막 및 그 제조방법
KR950021402A (ko) 트렌치형 소자분리막 형성방법
KR960026616A (ko) 반도체소자의 소자분리 산화막의 제조방법
KR960002471A (ko) 실리콘-온-인슐레이터(soi) 소자의 제조방법 및 그 구조
KR970053394A (ko) 반도체 장치의 트렌치 소자분리 방법
KR960026620A (ko) 보이드(Void)를 이용한 반도체 소자분리 방법
KR960002740A (ko) 반도체소자의 제조방법
KR960043104A (ko) 반도체 장치의 소자분리 방법
KR950030304A (ko) 반도체소자의 소자분리산화막 형성방법
JPS59124143A (ja) 半導体集積回路の製造方法
KR970003823A (ko) 반도체 소자의 소자분리막 형성방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060720

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee