KR960002740A - 반도체소자의 제조방법 - Google Patents

반도체소자의 제조방법 Download PDF

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Publication number
KR960002740A
KR960002740A KR1019940014247A KR19940014247A KR960002740A KR 960002740 A KR960002740 A KR 960002740A KR 1019940014247 A KR1019940014247 A KR 1019940014247A KR 19940014247 A KR19940014247 A KR 19940014247A KR 960002740 A KR960002740 A KR 960002740A
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KR
South Korea
Prior art keywords
oxide film
semiconductor device
film
manufacturing
device isolation
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KR1019940014247A
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English (en)
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KR0123843B1 (ko
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김승준
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김주용
현대전자산업 주식회사
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Priority to KR1019940014247A priority Critical patent/KR0123843B1/ko
Publication of KR960002740A publication Critical patent/KR960002740A/ko
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Publication of KR0123843B1 publication Critical patent/KR0123843B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)

Abstract

본 발명은 반도체소자의 제조공정시 반도체소자를 평탄화시켜 후속공정을 용이하게 함과 동시에 높은 전압 인가 시에도 견딜 수 있어 고집적화를 가능하게 하는 반도체소자의 제조방법에 관한 것으로, 마스크 공정으로 트렌치를 형성하고 고농도의 N형 불순물과 고농도의 P형 불순물영역이 서로 접합되지 않도록 함으로써 반도체소자의 접합 브레이크다운 전압을 증가시키고 주변회로부에 소자분리산화막을 셀부 보다 두껍게 형성함으로써 반도체소자의 신뢰성을 향상시키고 반도체소자의 고집적화를 가능하게 하는 기술이다.

Description

반도체소자의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제5도는 본 발명의 실시예에 의한 반도체소자의 제조공정을 도시한 단면도.
* 도면의 주요부분에 대한 부호의 설명
1 : 반도체기판 3 : 제1산화막
5 : 질화막 7 : 제1감광막패턴
9 : 제2감광막패턴 11 : 고농도 P형 불순물
13 : 제1소자분리산화막 12 : 제2소자분리산화막
17 : 제2산화막 30 : 제1트렌치
40 : 제2트렌치 50 : 셀부
60 : 주변회로부

Claims (4)

  1. 반도체소자의 제조방법에 있어서, 반도체기판 상부에 제1산화막 및 질화막을 순차적으로 증착하고 그 상부에 제1감광막패턴을 형성하는 공정과, 상기 제1감광막패턴을 마스크로 하여 상기 질화막과 제1산화막 그리고 반도체기판을 일정 깊이 식각함으로써 제1,2트렌치를 형성하고 상기 제1감광막패턴을 제거하는 공정과, 전체 구조상부에 상기 제2트렌치의 양끝부분부터 바깥쪽을 전부 도포하는 제2감광막패턴을 형성하고 전체 구조상부에 고농도의 불순물이온을 주입하는 공정과, 상기 제2감광막패턴을 제거하고 제1,2소자분리산화막을 성장시키는 공정과, 전체 구조상부에 제2산화막을 일정 두께 증착하는 공정과, 상기 제2산화막을 평면 식각하여 평탄화시키고 상기 질화막을 제거함으로써 트렌치구조의 소자분리산화막을 형성하는 공정을 포함하는 반도체소자의 제조방법.
  2. 제1항에 있어서, 상기 제2트렌치는 주변회로부 전체에 폭이 넓게 형성하는 것을 특징으로 하는 반도체소자의 제조방법.
  3. 제1항에 있어서, 상기 제2소자분리산화막은 상기 제1소자분리산화막보다 7-8배 정도 두껍게 형성하는 것을 특징으로 하는 반도체소자의 제조방법.
  4. 제1항에 있어서, 상기 제2산화막은 CVD 산화막을 사용하는 것을 특징으로 하는 반도체소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940014247A 1994-06-22 1994-06-22 반도체소자의 제조방법 KR0123843B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940014247A KR0123843B1 (ko) 1994-06-22 1994-06-22 반도체소자의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940014247A KR0123843B1 (ko) 1994-06-22 1994-06-22 반도체소자의 제조방법

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KR960002740A true KR960002740A (ko) 1996-01-26
KR0123843B1 KR0123843B1 (ko) 1997-11-25

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100443126B1 (ko) * 2002-08-19 2004-08-04 삼성전자주식회사 트렌치 구조물 및 이의 형성 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100443126B1 (ko) * 2002-08-19 2004-08-04 삼성전자주식회사 트렌치 구조물 및 이의 형성 방법

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