KR20040029588A - 반도체소자의 제조방법 - Google Patents
반도체소자의 제조방법 Download PDFInfo
- Publication number
- KR20040029588A KR20040029588A KR1020020059895A KR20020059895A KR20040029588A KR 20040029588 A KR20040029588 A KR 20040029588A KR 1020020059895 A KR1020020059895 A KR 1020020059895A KR 20020059895 A KR20020059895 A KR 20020059895A KR 20040029588 A KR20040029588 A KR 20040029588A
- Authority
- KR
- South Korea
- Prior art keywords
- region
- forming
- silicon substrate
- nitride film
- memory cell
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (3)
- 필드산화막에 의해 고전압 트랜지스터 형성영역과 메모리 셀 영역이 정의되어 있는 실리콘기판의 메모리 셀 영역의 상부에 제 1 질화막을 형성하는 단계와;상기 고전압 트랜지스터 형성영역 상부에 게이트 산화막을 형성하는 단계와;상기 제 1 질화막을 제거한 다음 결과물 전면에 제 2 질화막을 형성한 다음 메모리 셀 영역 상부의 제 2 질화막을 선택적으로 제거하여 BN 구조 형성영역을 형성하는 단계와;상기 제 2 질화막을 이온주입 마스크로 하여 메모리 셀 영역의 실리콘기판 내에 BN 이온을 주입하는 단계와;상기 BN 이온이 주입된 실리콘기판에 BN 옥시데이션 공정을 진행하여 BN 구조를 형성하는 단계와;상기 제 2 질화막을 제거한 다음 게이트산화막 상부에 폴리를 증착하여 게이트 패턴을 형성하는 단계와;상기 게이트 패턴을 이온주입 마스크로 실리콘기판 내에 불순물을 주입하여 소오스/드레인 불순물 확산영역을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1항에 있어서, 상기 제 2 질화막은 질화물을 1000 ~ 1500Å 증착하여 형성하는 것을 특징으로 하는 반도체소자의 제조방법.
- 제 1항에 있어서, 상기 게이트산화막은 400 ~ 600Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 제조방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020059895A KR100929422B1 (ko) | 2002-10-01 | 2002-10-01 | 반도체소자의 제조방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020020059895A KR100929422B1 (ko) | 2002-10-01 | 2002-10-01 | 반도체소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040029588A true KR20040029588A (ko) | 2004-04-08 |
KR100929422B1 KR100929422B1 (ko) | 2009-12-03 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020020059895A KR100929422B1 (ko) | 2002-10-01 | 2002-10-01 | 반도체소자의 제조방법 |
Country Status (1)
Country | Link |
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KR (1) | KR100929422B1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100664658B1 (ko) * | 2004-04-28 | 2007-01-04 | 삼성엔지니어링 주식회사 | 유류 분해 활성 측정용 마이크로어레이 및 그를 이용한유류 분해 활성을 분석하는 방법 |
KR101110178B1 (ko) * | 2004-07-19 | 2012-01-31 | 매그나칩 반도체 유한회사 | 고전압 트랜지스터의 제조방법 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100275816B1 (ko) * | 1993-10-27 | 2001-03-02 | 김영환 | 플레쉬 메모리 및 그 제조방법 |
-
2002
- 2002-10-01 KR KR1020020059895A patent/KR100929422B1/ko active IP Right Grant
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100664658B1 (ko) * | 2004-04-28 | 2007-01-04 | 삼성엔지니어링 주식회사 | 유류 분해 활성 측정용 마이크로어레이 및 그를 이용한유류 분해 활성을 분석하는 방법 |
KR101110178B1 (ko) * | 2004-07-19 | 2012-01-31 | 매그나칩 반도체 유한회사 | 고전압 트랜지스터의 제조방법 |
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Publication number | Publication date |
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KR100929422B1 (ko) | 2009-12-03 |
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