KR960011726A - 마이크로프로세서 - Google Patents

마이크로프로세서 Download PDF

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Publication number
KR960011726A
KR960011726A KR1019950030591A KR19950030591A KR960011726A KR 960011726 A KR960011726 A KR 960011726A KR 1019950030591 A KR1019950030591 A KR 1019950030591A KR 19950030591 A KR19950030591 A KR 19950030591A KR 960011726 A KR960011726 A KR 960011726A
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KR
South Korea
Prior art keywords
microprocessor
card
memory
bus
cards
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Application number
KR1019950030591A
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English (en)
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KR100353348B1 (ko
Inventor
시게즈미 마쯔이
이꾸야 가와사끼
스스무 나리따
마사또 네모또
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
사까이 아끼라
히다찌엔지니어링 가부시끼가이샤
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Priority claimed from JP6251394A external-priority patent/JPH0895943A/ja
Priority claimed from JP26087395A external-priority patent/JP3862031B2/ja
Application filed by 가나이 쯔또무, 가부시끼가이샤 히다찌세이사꾸쇼, 사까이 아끼라, 히다찌엔지니어링 가부시끼가이샤 filed Critical 가나이 쯔또무
Publication of KR960011726A publication Critical patent/KR960011726A/ko
Application granted granted Critical
Publication of KR100353348B1 publication Critical patent/KR100353348B1/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microcomputers (AREA)

Abstract

마이크로프로세서에 관한 것으로써, 사용상 편리하고, PC카드인터페이스를 갖는 퍼스널컴퓨터등의 설계공정수 및 외부부품을 삭감하여 저코스트화를 도모하기 위해, 퍼스널컴퓨터등에 내장되는 마이크로프로세서에 대기제어레지스터 WCRI 및 WCR2등의 제어레지스터를 포함하고, 또한 ROM, 버스트ROM, SRAM, PSRAM, DRAM 및 동기DRAM등의 각종 반도체메모리나 메모리카드 및 I/O카드등의 PC카드의 인터페이스를 병행제어할 수 있는 버스상태컨트롤러BSC릎 마련하고, 버스상태컨크롤러BSC에 동기DRAM접속시에 있어서의 PC카드의 기동신호(-OE,-WE)의 세트업시간을 제어하기 위한 제어레지스터(PCR)가 마련되고, 또 외부 버스의 어드레스공간을 소정수의 에리어로 분할하고, 각 에리어에 반도체메모리 또는 PC카드를 고정적으로 할당함과 동시에 마이크로프로세서에 논리어드레스를 물리어드레스로 변환하는 메모리관리유닛을 마련한다.
이러한 마이크로프로세서에 의해, 물리어드레스에 의한 제약을 받지 않으며, 그리고 인터페이스제어를 위한 외부부품을 삭감하면서 각종 반도체메모리 및 PC카드를 직접 또한 동시에 마이크로프로세서의 외수버스에 결합할 수 있다.

Description

마이크로프로세서
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 관한 마이크로프로세서를 포함하는 퍼스널컴퓨터의 1실시예를 도시한 시스템구성도.
제2도는 제1도의 퍼스널컴퓨터의 1실시예를 도시한 외관구성도.

Claims (8)

  1. 반도체메모리 및 PC카드를 직접 결합가능하게 하는 인터페이스회로를 포함하는 마이크로프로세서.
  2. 제1항에 있어서, 상기 인터페이스회로는 상기 마이크로프로세서의 외부버스로 출력될 여러개의 제어신호를 작성하고, 상기 반도체베모리는 ROM, 버스트ROM, SRAM, PSRAM, DRAM 및 동기DRAM을 포함하고, 상기 PC카드는 메모리카드 및 I/O카드를 포함하는 마이크로프로세서.
  3. 제2항에 있어서, 상기 외부버스의 어드레스공간은 여러개의 에리어로 분할되고, 상기 여러개의 에리어의 각각은 소정의 반도체메모리 또는 PC카드에 고정적으로 할당되고, 상기 마이크로프로세서는 그 내부에 있어서의 논리어드레스를 상기 외부버스에 있어서의 물리어드레스로 변환하는 메모리관리유닛을 구비하는 마이므로프로세서.
  4. 제3항에 있어서, 상기 외부버스에는 상기 여러종류의 반도체메모리의 일부 또는 전부와 메모리카드 및 I/O카드를 동시에 결합할 수 있는 마이크로프로세서.
  5. 제4항에 있어서, 상기 I/O카드는 메모리로써의 기능을 갖고, 그 입출력장치로써 기능하는 경우의 물리어드레스는 메모리로써 기능하는 경우의 물리어드레스와는 독립적으로 할당되는 마이크로프로세서.
  6. 제3항에 있어서, 상기 반도체메모리 또는 PC카드사이의 인터페이스제어세 사용되고 상기 에리어의 각각에 할당된 반도체메모리 또는 PC카드의 종류 및 그 동작조건등을 설정하기 위한 레지스터를 포함하는 버스상태컨트롤러를 또 구비하는 마이크로프로세서.
  7. 제6항에 있어서, 상기 반도체메모리 및 PC카드의 일부 또는 전부는 일련의 어드레스를 연속액세스하기 위한 버스트모드를 갖고, 상기 버스상태컨트롤러는 이 버스트모드를 위한 어드레스생성회로를 갖는 마이크로프로세서.
  8. 제7항에 있어서, 상기 버스상태컨트롤러는 상태머신으로 이루어지는 것을 특징으로 하는 마이크로 프로세서.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950030591A 1994-09-20 1995-09-19 마이크로프로세서 KR100353348B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP6251394A JPH0895943A (ja) 1994-09-20 1994-09-20 マイクロプロセッサ
JP94-251394 1994-09-20
JP95-085931 1995-03-20
JP8593195 1995-03-20
JP26087395A JP3862031B2 (ja) 1995-03-20 1995-09-13 マイクロプロセッサ
JP95-260873 1995-09-13

Publications (2)

Publication Number Publication Date
KR960011726A true KR960011726A (ko) 1996-04-20
KR100353348B1 KR100353348B1 (ko) 2003-01-06

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US6594720B1 (en) 2003-07-15
US20030149821A1 (en) 2003-08-07
US5848247A (en) 1998-12-08
US6049844A (en) 2000-04-11
KR100353348B1 (ko) 2003-01-06
US6792493B2 (en) 2004-09-14

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