KR940012146A - Cpu와 승산기를 갖는 반도체집적회로 - Google Patents

Cpu와 승산기를 갖는 반도체집적회로 Download PDF

Info

Publication number
KR940012146A
KR940012146A KR1019930023160A KR930023160A KR940012146A KR 940012146 A KR940012146 A KR 940012146A KR 1019930023160 A KR1019930023160 A KR 1019930023160A KR 930023160 A KR930023160 A KR 930023160A KR 940012146 A KR940012146 A KR 940012146A
Authority
KR
South Korea
Prior art keywords
bus
cpu
multiplier
integrated circuit
data
Prior art date
Application number
KR1019930023160A
Other languages
English (en)
Other versions
KR100306107B1 (ko
Inventor
가즈마사 기시
시게끼 마스무라
히데오 나까무라
고끼 노구찌
순페이 가와사끼
야스시 아까오
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
스즈끼 진이찌로
히다찌 초엘에스아이 엔지니어링 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쯔또무, 가부시끼가이샤 히다찌세이사꾸쇼, 스즈끼 진이찌로, 히다찌 초엘에스아이 엔지니어링 가부시끼가이샤 filed Critical 가나이 쯔또무
Publication of KR940012146A publication Critical patent/KR940012146A/ko
Application granted granted Critical
Publication of KR100306107B1 publication Critical patent/KR100306107B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Microcomputers (AREA)

Abstract

본 발명은 중앙처리장치(CPU)와 메모리를 갖는 논리 LSI에 관한 것이고, 특히 고속신호처리를 필요로 하는 싱글칩 마이크로컴퓨터에 관한 것이며, 승산기의 목표성는에 합치한 설계변경이 용이함과 동시에 메모리와 승산기의 사이에서 데이타를 직접 전송할수 있는 반도체집적회로를 제공하기 위해, CPU(1)로부터 공급된 어드레스에 의해 액세스되는 메모리(3), 상기 버스(4)를 거쳐서 상기CPU(1)에 접속된 승산기(2), 상기CPU(1)로부터 상기 버스(5)에 액세스어드레스를 출력하는 것에 의해, 상기버스(4)를 거쳐서 상기 메모리(3)으로부터 데이타를 기드하는 사이에, 상기 리드데이타에 관한 승산명령의 코맨드를 CPU(1)로부터 상기 승산기(2)에 전송하는 코맨드신호선(6)을 칩상에 구비하는 것이다.
이와 같이 구성하는 거에 의해, 목표성능에 따라서 칩사이즈를 최소화할 수가 있고, 고속화의 효과가 있다.

Description

CPU와 승산기를 갖는 반도체집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 내장된 승산기를 구비한 본 발명의 실시예에 의한 싱글 침 마이크로컴퓨터의 내부 블럭도,
제2도는 제1도의 실시예의 싱글칩 마이크로컴퓨터의 동작을 설명하기 위한 타이밍도,
제3도는 본 발명에 앞서 본 발명자들에 의해 연구된 싱글칩 마이크로 컴퓨터의 내부 블럭도의 일예.

Claims (4)

  1. 중앙처리장치(CPU), 상기 CPU로부터 어드레스와 데이타가 전달되는 버스, 상기 버스에 접속되어 상기 CPU로부터 공급된 어드레스에 의해 액세스되는 메모리, 상기 버스를 거쳐서 상기 CPU에 접속된 승산기, 상기 CPU로부터 상기 버스에 액세스어드레스를 출력하는 것에 의해, 상기 버스를 거쳐서 상기 메모리로부터 데이타를 리드하는 사이에, 상기 리드데이타에 관한 승산명령의 코맨드를 상기 CPU로부터 상기 승산기에 전송하는 코맨드 신호선을 포함하는 반도체 집적회로칩.
  2. 제1항에 있어서, 상기 승산기가 상기 승산명령의 반복연산을 실행하고 있는 것을 나타내는 상태신호를 상기 승산기는 출력하고, 상기 상태신호에 응답하여 상기CPU로부터 상기 코맨드신호선으로의 다음 코맨드발행에 관계하는 버스사이클을 연장하는 버스사이클 제어회로가 상기 CPU에 접속되어 있는 반도체 집적회로칩.
  3. 제1항에 있어서, 상기 버스는 어드레스버스와 데이타버스를 포함하는 반도체 집적회로칩.
  4. 제2항에 있어서, 상기 버스는 어드레스버스와 데이타버스를 포함하는 반도체 집적회로칩.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930023160A 1992-11-06 1993-11-03 Cpu와승산기를갖는반도체집적회로 KR100306107B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-296778 1992-11-06
JP29677892A JP3231429B2 (ja) 1992-11-06 1992-11-06 中央処理装置と乗算器とを有する半導体集積回路装置

Publications (2)

Publication Number Publication Date
KR940012146A true KR940012146A (ko) 1994-06-22
KR100306107B1 KR100306107B1 (ko) 2001-11-30

Family

ID=17838015

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930023160A KR100306107B1 (ko) 1992-11-06 1993-11-03 Cpu와승산기를갖는반도체집적회로

Country Status (3)

Country Link
US (1) US5832248A (ko)
JP (1) JP3231429B2 (ko)
KR (1) KR100306107B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102143339B1 (ko) 2019-07-17 2020-08-11 (유)다시 폐오일캔 압축장치

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5867726A (en) * 1995-05-02 1999-02-02 Hitachi, Ltd. Microcomputer
JP3655403B2 (ja) * 1995-10-09 2005-06-02 株式会社ルネサステクノロジ データ処理装置
US6615370B1 (en) 1999-10-01 2003-09-02 Hitachi, Ltd. Circuit for storing trace information
US6557119B1 (en) 1999-10-01 2003-04-29 Stmicroelectronics Limited Microcomputer debug architecture and method
US7072817B1 (en) * 1999-10-01 2006-07-04 Stmicroelectronics Ltd. Method of designing an initiator in an integrated circuit
US6408381B1 (en) 1999-10-01 2002-06-18 Hitachi, Ltd. Mechanism for fast access to control space in a pipeline processor
US6826191B1 (en) 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US6449712B1 (en) 1999-10-01 2002-09-10 Hitachi, Ltd. Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
US6496905B1 (en) 1999-10-01 2002-12-17 Hitachi, Ltd. Write buffer with burst capability
US6732307B1 (en) 1999-10-01 2004-05-04 Hitachi, Ltd. Apparatus and method for storing trace information
US6629207B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method for loading instructions or data into a locked way of a cache memory
US6772325B1 (en) * 1999-10-01 2004-08-03 Hitachi, Ltd. Processor architecture and operation for exploiting improved branch control instruction
US6928073B2 (en) * 1999-10-01 2005-08-09 Stmicroelectronics Ltd. Integrated circuit implementing packet transmission
US6530047B1 (en) 1999-10-01 2003-03-04 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6349371B1 (en) 1999-10-01 2002-02-19 Stmicroelectronics Ltd. Circuit for storing information
US6457118B1 (en) 1999-10-01 2002-09-24 Hitachi Ltd Method and system for selecting and using source operands in computer system instructions
US7260745B1 (en) 1999-10-01 2007-08-21 Stmicroelectronics Ltd. Detection of information on an interconnect
US7793261B1 (en) 1999-10-01 2010-09-07 Stmicroelectronics Limited Interface for transferring debug information
US6693914B1 (en) 1999-10-01 2004-02-17 Stmicroelectronics, Inc. Arbitration mechanism for packet transmission
US6684348B1 (en) 1999-10-01 2004-01-27 Hitachi, Ltd. Circuit for processing trace information
US6918065B1 (en) 1999-10-01 2005-07-12 Hitachi, Ltd. Method for compressing and decompressing trace information
US6546480B1 (en) 1999-10-01 2003-04-08 Hitachi, Ltd. Instructions for arithmetic operations on vectored data
US6820195B1 (en) 1999-10-01 2004-11-16 Hitachi, Ltd. Aligning load/store data with big/little endian determined rotation distance control
US6567932B2 (en) 1999-10-01 2003-05-20 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6351803B2 (en) 1999-10-01 2002-02-26 Hitachi Ltd. Mechanism for power efficient processing in a pipeline processor
US6298394B1 (en) 1999-10-01 2001-10-02 Stmicroelectronics, Ltd. System and method for capturing information on an interconnect in an integrated circuit
US6629115B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method and apparatus for manipulating vectored data
US6412043B1 (en) 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6598177B1 (en) 1999-10-01 2003-07-22 Stmicroelectronics Ltd. Monitoring error conditions in an integrated circuit
US6553460B1 (en) 1999-10-01 2003-04-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6859891B2 (en) 1999-10-01 2005-02-22 Stmicroelectronics Limited Apparatus and method for shadowing processor information
US6590907B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics Ltd. Integrated circuit with additional ports
US6460174B1 (en) 1999-10-01 2002-10-01 Stmicroelectronics, Ltd. Methods and models for use in designing an integrated circuit
US6601189B1 (en) 1999-10-01 2003-07-29 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6591369B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics, Ltd. System and method for communicating with an integrated circuit
US6779145B1 (en) 1999-10-01 2004-08-17 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6701405B1 (en) 1999-10-01 2004-03-02 Hitachi, Ltd. DMA handshake protocol
US6463553B1 (en) 1999-10-01 2002-10-08 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US7266728B1 (en) 1999-10-01 2007-09-04 Stmicroelectronics Ltd. Circuit for monitoring information on an interconnect
US6542983B1 (en) 1999-10-01 2003-04-01 Hitachi, Ltd. Microcomputer/floating point processor interface and method
US6665816B1 (en) 1999-10-01 2003-12-16 Stmicroelectronics Limited Data shift register
US6633971B2 (en) 1999-10-01 2003-10-14 Hitachi, Ltd. Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline
US6487683B1 (en) 1999-10-01 2002-11-26 Stmicroelectronics Limited Microcomputer debug architecture and method
US7000078B1 (en) * 1999-10-01 2006-02-14 Stmicroelectronics Ltd. System and method for maintaining cache coherency in a shared memory system
US6574651B1 (en) 1999-10-01 2003-06-03 Hitachi, Ltd. Method and apparatus for arithmetic operation on vectored data
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd ２つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US6412047B2 (en) 1999-10-01 2002-06-25 Stmicroelectronics, Inc. Coherency protocol
US6502210B1 (en) 1999-10-01 2002-12-31 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6434665B1 (en) 1999-10-01 2002-08-13 Stmicroelectronics, Inc. Cache memory store buffer
JP2023543466A (ja) * 2020-09-30 2023-10-16 ホアウェイ・テクノロジーズ・カンパニー・リミテッド 回路、チップ、および電子デバイス

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1082802B (it) * 1977-05-02 1985-05-21 Cselt Centro Studi Lab Telecom Unita microprogrammata per una apparecchiatura di terminazione di rete in trasmissione dati integrata con dispositivo di mo demodulazione e per la relativa apparecchiatura di centrale
EP0392133B1 (en) * 1982-02-11 1997-10-08 Texas Instruments Incorporated High-speed multiplier for a microcomputer used in a digital signal processing system
NL8304186A (nl) * 1983-12-06 1985-07-01 Philips Nv Geintegreerde processor voor het verwerken van woordsgewijze ontvangbare informatie.
FI855180A (fi) * 1985-01-18 1986-07-19 Nissan Chemical Ind Ltd Pyrazolsulfonamidderivat, foerfarande foer dess framstaellande och det innehaollande ograesgift.
JPS62214464A (ja) * 1986-03-17 1987-09-21 Hitachi Ltd データ処理システム
JPH0663882B2 (ja) * 1986-12-19 1994-08-22 工業技術院長 圧覚センサ出力信号前処理装置
US4876644A (en) * 1987-10-30 1989-10-24 International Business Machines Corp. Parallel pipelined processor
AU616213B2 (en) * 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
US5056015A (en) * 1988-03-23 1991-10-08 Du Pont Pixel Systems Limited Architectures for serial or parallel loading of writable control store
US5086407A (en) * 1989-06-05 1992-02-04 Mcgarity Ralph C Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation
JPH03167649A (ja) * 1989-11-28 1991-07-19 Nec Corp ウエイト・サイクル制御装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102143339B1 (ko) 2019-07-17 2020-08-11 (유)다시 폐오일캔 압축장치

Also Published As

Publication number Publication date
US5832248A (en) 1998-11-03
JP3231429B2 (ja) 2001-11-19
JPH06149545A (ja) 1994-05-27
KR100306107B1 (ko) 2001-11-30

Similar Documents

Publication Publication Date Title
KR940012146A (ko) Cpu와 승산기를 갖는 반도체집적회로
US4727491A (en) Personal computer having normal and high speed execution modes
US4835681A (en) Personal computer having normal and high speed execution modes
US20070055813A1 (en) Accessing external memory from an integrated circuit
JPH04230544A (ja) ダイナミックメモリシステムのタイミングを動的に設定するデータ処理装置
US6334166B1 (en) Processor system using synchronous dynamic memory
JPS6297036A (ja) 計算機システム
KR890005622A (ko) 단일칩 마이크로 컴퓨터
US4358826A (en) Apparatus for enabling byte or word addressing of storage organized on a word basis
JPS6045828A (ja) シングルチツプマイコン
KR950012245A (ko) 사용자 설계 회로를 갖는 단일 칩 마이크로컴퓨터
KR970067364A (ko) 멀티모드 캐시 메모리
JPS5868286A (ja) キヤツシユメモリおよびその作動方法
KR970066899A (ko) 데이터 프로세서, 데이터 처리 시스템, 및 데이터 프로세서를 이용한 외부장치로의 액세스 방법
US6219740B1 (en) Information processing device
KR100252508B1 (ko) 통신처리시스템의 프로세서 보드에서 롬 인터페이스장치
KR100488103B1 (ko) 중앙 처리 장치의 고성능 처리를 위한 메모리 주소 맵핑회로
KR960018958A (ko) 다중 프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치
JPH0542525Y2 (ko)
KR100452332B1 (ko) 데이터 읽기 및 쓰기 속도 개선 방법
KR100446282B1 (ko) 시스템 버스 인터페이스 회로
SU1695381A1 (ru) Запоминающее устройство
KR920002073B1 (ko) 데이터 메모리 확장장치
KR100258691B1 (ko) 통신처리시스템의 프로세서보드에서 데이터 폭 조절장치
JP2581484B2 (ja) データ処理システム

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080721

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee