KR960005864A - 미세패턴 형성방법 - Google Patents
미세패턴 형성방법 Download PDFInfo
- Publication number
- KR960005864A KR960005864A KR1019940016980A KR19940016980A KR960005864A KR 960005864 A KR960005864 A KR 960005864A KR 1019940016980 A KR1019940016980 A KR 1019940016980A KR 19940016980 A KR19940016980 A KR 19940016980A KR 960005864 A KR960005864 A KR 960005864A
- Authority
- KR
- South Korea
- Prior art keywords
- photoresist
- photoresist film
- exposed
- pattern
- mask
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract 13
- 230000007261 regionalization Effects 0.000 title 1
- 125000006850 spacer group Chemical group 0.000 claims abstract 4
- 239000004065 semiconductor Substances 0.000 claims abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 claims 13
- 239000000758 substrate Substances 0.000 claims 3
- 238000001312 dry etching Methods 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/947—Subphotolithographic processing
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 감광막에 1차 노광을 행한 뒤 2차 노광시 마스크를 쉬프트시킨 뒤 노광을 행하여 감광막패턴을 형성하고, 쉬프트 노광시 얻어지는 감광막 패턴의 단차에 스페이서를 형성하고, 스페이서를 이용하여 미세한 패턴을 형성하는 방법에 관한 것이다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제8도는 본 발명에 의해 미세패턴 형성단계를 도시한 단면도.
Claims (5)
- 반도체 소자의 미세패턴 형성방법에 있어서, 기판 상부에 하부층을 형성하고, 그 상부에 감광막을 도포한 다음, 마스크를 이용하고, 1/2Eth 정도가 되는 노광에너지로 감광막을 1차 노광시키는 단계와, 마스크를 일정거리 쉬프트하여 1/2Eth 되는 노광에너지로 감광막을 2차 노광시키는 단계와, 노광된 감광막을 습식현상하여 한번 노광된 지역과 노광되지 않은 지역의 두께가 다른 감광막패턴을 형성하는 단계와, 전체 구조 상부에 절연층을 증착하고, 전면 식각공정으로 상기 감광막패턴의 측벽에 절연층 스페이서를 형성하는 단계와, 상기 절연층 스페이서를 마스크로 사용하여 노출되는 감광막패턴을 건식식각하고 계속하여 노출되는 하부층을 건식식각하여 하부층 패턴을 형성하는 단계를 포함하는 미세패턴 형성방법.
- 제1항에 있어서, 상기 1/2Eth 되는 노광에너지로 감광막을 노광시킨 다음, 현상공정을 진행할 경우 감광막의 1/2 두께가 남도록 하는 것을 특징으로 하는 미세패턴 형성방법.
- 제1항에 있어서, 상기 1차 노광공정과 2차 노광공정에서 공통으로 노광되는 지역은 완전히 감광막이 제거되고, 1차 또는 2차 노광에서 한번 노광되는 지역은 1/2 두께의 감광막이 남도록 감광막패턴이 형성되는 것을 특징으로 하는 미세패턴 형성방법.
- 제1항에 있어서, 상기 절연층 스페이서로 사용되는 물질은 실리콘-산화물계로 감광막과의 식각 선택비는 20 : 1 이상인 것을 특징으로 하는 미세패턴 형성방법.
- 제1항에 있어서, 상기 마스크를 일정거리 쉬프트하는 대신에 기판을 쉬프트시키는 것을 특징으로 하는 미세패턴 형성방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940016980A KR970007173B1 (ko) | 1994-07-14 | 1994-07-14 | 미세패턴 형성방법 |
US08/501,605 US5593813A (en) | 1994-07-14 | 1995-07-12 | Method for forming submicroscopic patterns |
GB9514186A GB2291266B (en) | 1994-07-14 | 1995-07-12 | Improvements in or relating to the formation of semiconductor devices |
CN95107566A CN1075245C (zh) | 1994-07-14 | 1995-07-14 | 形成超微细图案的方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940016980A KR970007173B1 (ko) | 1994-07-14 | 1994-07-14 | 미세패턴 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960005864A true KR960005864A (ko) | 1996-02-23 |
KR970007173B1 KR970007173B1 (ko) | 1997-05-03 |
Family
ID=19387985
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940016980A KR970007173B1 (ko) | 1994-07-14 | 1994-07-14 | 미세패턴 형성방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5593813A (ko) |
KR (1) | KR970007173B1 (ko) |
CN (1) | CN1075245C (ko) |
GB (1) | GB2291266B (ko) |
Cited By (1)
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---|---|---|---|---|
KR100277490B1 (ko) * | 1997-11-28 | 2001-01-15 | 전주범 | 반도체소자의미세패턴형성방법 |
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CN112882355B (zh) * | 2021-03-09 | 2023-05-23 | 上海大溥实业有限公司 | 使光刻线条变窄的方法及光刻机 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4379833A (en) * | 1981-12-31 | 1983-04-12 | International Business Machines Corporation | Self-aligned photoresist process |
DE3337315A1 (de) * | 1982-10-13 | 1984-04-19 | Tokyo Ohka Kogyo Co., Ltd., Kawasaki, Kanagawa | Zweifach-lichtempfindliche zusammensetzungen und verfahren zur erzeugung bildmustergemaesser photoresistschichten |
KR910010043B1 (ko) * | 1988-07-28 | 1991-12-10 | 한국전기통신공사 | 스페이서를 이용한 미세선폭 형성방법 |
KR930008139B1 (en) * | 1990-08-30 | 1993-08-26 | Samsung Electronics Co Ltd | Method for preparation of pattern |
US5407785A (en) * | 1992-12-18 | 1995-04-18 | Vlsi Technology, Inc. | Method for generating dense lines on a semiconductor wafer using phase-shifting and multiple exposures |
-
1994
- 1994-07-14 KR KR1019940016980A patent/KR970007173B1/ko not_active IP Right Cessation
-
1995
- 1995-07-12 US US08/501,605 patent/US5593813A/en not_active Expired - Lifetime
- 1995-07-12 GB GB9514186A patent/GB2291266B/en not_active Expired - Fee Related
- 1995-07-14 CN CN95107566A patent/CN1075245C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100277490B1 (ko) * | 1997-11-28 | 2001-01-15 | 전주범 | 반도체소자의미세패턴형성방법 |
Also Published As
Publication number | Publication date |
---|---|
GB2291266B (en) | 1998-04-01 |
CN1075245C (zh) | 2001-11-21 |
GB9514186D0 (en) | 1995-09-13 |
CN1118936A (zh) | 1996-03-20 |
KR970007173B1 (ko) | 1997-05-03 |
US5593813A (en) | 1997-01-14 |
GB2291266A (en) | 1996-01-17 |
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