KR960005864A - 미세패턴 형성방법 - Google Patents

미세패턴 형성방법 Download PDF

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Publication number
KR960005864A
KR960005864A KR1019940016980A KR19940016980A KR960005864A KR 960005864 A KR960005864 A KR 960005864A KR 1019940016980 A KR1019940016980 A KR 1019940016980A KR 19940016980 A KR19940016980 A KR 19940016980A KR 960005864 A KR960005864 A KR 960005864A
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KR
South Korea
Prior art keywords
photoresist
photoresist film
exposed
pattern
mask
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Application number
KR1019940016980A
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English (en)
Other versions
KR970007173B1 (ko
Inventor
김형수
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940016980A priority Critical patent/KR970007173B1/ko
Priority to US08/501,605 priority patent/US5593813A/en
Priority to GB9514186A priority patent/GB2291266B/en
Priority to CN95107566A priority patent/CN1075245C/zh
Publication of KR960005864A publication Critical patent/KR960005864A/ko
Application granted granted Critical
Publication of KR970007173B1 publication Critical patent/KR970007173B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20Exposure; Apparatus therefor
    • G03F7/2022Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338Process specially adapted to improve the resolution of the mask
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/947Subphotolithographic processing

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 감광막에 1차 노광을 행한 뒤 2차 노광시 마스크를 쉬프트시킨 뒤 노광을 행하여 감광막패턴을 형성하고, 쉬프트 노광시 얻어지는 감광막 패턴의 단차에 스페이서를 형성하고, 스페이서를 이용하여 미세한 패턴을 형성하는 방법에 관한 것이다.

Description

미세패턴 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제8도는 본 발명에 의해 미세패턴 형성단계를 도시한 단면도.

Claims (5)

  1. 반도체 소자의 미세패턴 형성방법에 있어서, 기판 상부에 하부층을 형성하고, 그 상부에 감광막을 도포한 다음, 마스크를 이용하고, 1/2Eth 정도가 되는 노광에너지로 감광막을 1차 노광시키는 단계와, 마스크를 일정거리 쉬프트하여 1/2Eth 되는 노광에너지로 감광막을 2차 노광시키는 단계와, 노광된 감광막을 습식현상하여 한번 노광된 지역과 노광되지 않은 지역의 두께가 다른 감광막패턴을 형성하는 단계와, 전체 구조 상부에 절연층을 증착하고, 전면 식각공정으로 상기 감광막패턴의 측벽에 절연층 스페이서를 형성하는 단계와, 상기 절연층 스페이서를 마스크로 사용하여 노출되는 감광막패턴을 건식식각하고 계속하여 노출되는 하부층을 건식식각하여 하부층 패턴을 형성하는 단계를 포함하는 미세패턴 형성방법.
  2. 제1항에 있어서, 상기 1/2Eth 되는 노광에너지로 감광막을 노광시킨 다음, 현상공정을 진행할 경우 감광막의 1/2 두께가 남도록 하는 것을 특징으로 하는 미세패턴 형성방법.
  3. 제1항에 있어서, 상기 1차 노광공정과 2차 노광공정에서 공통으로 노광되는 지역은 완전히 감광막이 제거되고, 1차 또는 2차 노광에서 한번 노광되는 지역은 1/2 두께의 감광막이 남도록 감광막패턴이 형성되는 것을 특징으로 하는 미세패턴 형성방법.
  4. 제1항에 있어서, 상기 절연층 스페이서로 사용되는 물질은 실리콘-산화물계로 감광막과의 식각 선택비는 20 : 1 이상인 것을 특징으로 하는 미세패턴 형성방법.
  5. 제1항에 있어서, 상기 마스크를 일정거리 쉬프트하는 대신에 기판을 쉬프트시키는 것을 특징으로 하는 미세패턴 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940016980A 1994-07-14 1994-07-14 미세패턴 형성방법 KR970007173B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019940016980A KR970007173B1 (ko) 1994-07-14 1994-07-14 미세패턴 형성방법
US08/501,605 US5593813A (en) 1994-07-14 1995-07-12 Method for forming submicroscopic patterns
GB9514186A GB2291266B (en) 1994-07-14 1995-07-12 Improvements in or relating to the formation of semiconductor devices
CN95107566A CN1075245C (zh) 1994-07-14 1995-07-14 形成超微细图案的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940016980A KR970007173B1 (ko) 1994-07-14 1994-07-14 미세패턴 형성방법

Publications (2)

Publication Number Publication Date
KR960005864A true KR960005864A (ko) 1996-02-23
KR970007173B1 KR970007173B1 (ko) 1997-05-03

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KR1019940016980A KR970007173B1 (ko) 1994-07-14 1994-07-14 미세패턴 형성방법

Country Status (4)

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US (1) US5593813A (ko)
KR (1) KR970007173B1 (ko)
CN (1) CN1075245C (ko)
GB (1) GB2291266B (ko)

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KR100277490B1 (ko) * 1997-11-28 2001-01-15 전주범 반도체소자의미세패턴형성방법

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CN1075245C (zh) 2001-11-21
GB9514186D0 (en) 1995-09-13
CN1118936A (zh) 1996-03-20
KR970007173B1 (ko) 1997-05-03
US5593813A (en) 1997-01-14
GB2291266A (en) 1996-01-17

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