KR950034532A - - Google Patents

Info

Publication number
KR950034532A
KR950034532A KR19950010065A KR19950010065A KR950034532A KR 950034532 A KR950034532 A KR 950034532A KR 19950010065 A KR19950010065 A KR 19950010065A KR 19950010065 A KR19950010065 A KR 19950010065A KR 950034532 A KR950034532 A KR 950034532A
Authority
KR
South Korea
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR19950010065A
Other languages
Korean (ko)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR950034532A publication Critical patent/KR950034532A/ko
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
KR19950010065A 1994-04-28 1995-04-27 Abandoned KR950034532A (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/234,100 US5565384A (en) 1994-04-28 1994-04-28 Self-aligned via using low permittivity dielectric

Publications (1)

Publication Number Publication Date
KR950034532A true KR950034532A (enExample) 1995-12-28

Family

ID=22879931

Family Applications (1)

Application Number Title Priority Date Filing Date
KR19950010065A Abandoned KR950034532A (enExample) 1994-04-28 1995-04-27

Country Status (6)

Country Link
US (1) US5565384A (enExample)
EP (1) EP0680084B1 (enExample)
JP (1) JPH0851154A (enExample)
KR (1) KR950034532A (enExample)
DE (1) DE69528409T2 (enExample)
TW (1) TW299484B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100518988B1 (ko) * 1996-04-29 2005-12-01 텍사스 인스트루먼츠 인코포레이티드 집적회로절연체및그제조방법

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US6278174B1 (en) * 1994-04-28 2001-08-21 Texas Instruments Incorporated Integrated circuit insulator and structure using low dielectric insulator material including HSQ and fluorinated oxide
US5488015A (en) * 1994-05-20 1996-01-30 Texas Instruments Incorporated Method of making an interconnect structure with an integrated low density dielectric
US7294578B1 (en) 1995-06-02 2007-11-13 Micron Technology, Inc. Use of a plasma source to form a layer during the formation of a semiconductor device
US6716769B1 (en) 1995-06-02 2004-04-06 Micron Technology, Inc. Use of a plasma source to form a layer during the formation of a semiconductor device
JPH0936226A (ja) * 1995-07-18 1997-02-07 Nec Corp 半導体装置およびその製造方法
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US5854131A (en) * 1996-06-05 1998-12-29 Advanced Micro Devices, Inc. Integrated circuit having horizontally and vertically offset interconnect lines
KR100192589B1 (ko) * 1996-08-08 1999-06-15 윤종용 반도체 장치 및 그 제조방법
US6136700A (en) * 1996-12-20 2000-10-24 Texas Instruments Incorporated Method for enhancing the performance of a contact
US6303488B1 (en) 1997-02-12 2001-10-16 Micron Technology, Inc. Semiconductor processing methods of forming openings to devices and substrates, exposing material from which photoresist cannot be substantially selectively removed
US6849557B1 (en) 1997-04-30 2005-02-01 Micron Technology, Inc. Undoped silicon dioxide as etch stop for selective etch of doped silicon dioxide
US6010957A (en) * 1997-06-25 2000-01-04 Advanced Micro Devices Semiconductor device having tapered conductive lines and fabrication thereof
JP3390329B2 (ja) * 1997-06-27 2003-03-24 日本電気株式会社 半導体装置およびその製造方法
GB2350931B (en) * 1997-06-27 2001-03-14 Nec Corp Method of manufacturing semiconductor device having multilayer wiring
US6048803A (en) * 1997-08-19 2000-04-11 Advanced Microdevices, Inc. Method of fabricating a semiconductor device having fluorine bearing oxide between conductive lines
US6875681B1 (en) * 1997-12-31 2005-04-05 Intel Corporation Wafer passivation structure and method of fabrication
US6143649A (en) * 1998-02-05 2000-11-07 Micron Technology, Inc. Method for making semiconductor devices having gradual slope contacts
KR100283028B1 (ko) * 1998-03-19 2001-03-02 윤종용 디램 셀 캐패시터의 제조 방법
JP2002510878A (ja) 1998-04-02 2002-04-09 アプライド マテリアルズ インコーポレイテッド 低ｋ誘電体をエッチングする方法
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US6175147B1 (en) * 1998-05-14 2001-01-16 Micron Technology Inc. Device isolation for semiconductor devices
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US6492276B1 (en) 1998-05-29 2002-12-10 Taiwan Semiconductor Manufacturing Company Hard masking method for forming residue free oxygen containing plasma etched layer
US6007733A (en) * 1998-05-29 1999-12-28 Taiwan Semiconductor Manufacturing Company Hard masking method for forming oxygen containing plasma etchable layer
US6232235B1 (en) * 1998-06-03 2001-05-15 Motorola, Inc. Method of forming a semiconductor device
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US6440863B1 (en) * 1998-09-04 2002-08-27 Taiwan Semiconductor Manufacturing Company Plasma etch method for forming patterned oxygen containing plasma etchable layer
US6174800B1 (en) 1998-09-08 2001-01-16 Taiwan Semiconductor Manufacturing Company Via formation in a poly(arylene ether) inter metal dielectric layer
US6187672B1 (en) * 1998-09-22 2001-02-13 Conexant Systems, Inc. Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing
US6245663B1 (en) * 1998-09-30 2001-06-12 Conexant Systems, Inc. IC interconnect structures and methods for making same
US6228758B1 (en) * 1998-10-14 2001-05-08 Advanced Micro Devices, Inc. Method of making dual damascene conductive interconnections and integrated circuit device comprising same
US6004883A (en) * 1998-10-23 1999-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Dual damascene patterned conductor layer formation method without etch stop layer
US6165898A (en) * 1998-10-23 2000-12-26 Taiwan Semiconductor Manufacturing Company Dual damascene patterned conductor layer formation method without etch stop layer
US6265308B1 (en) 1998-11-30 2001-07-24 International Business Machines Corporation Slotted damascene lines for low resistive wiring lines for integrated circuit
US6495468B2 (en) 1998-12-22 2002-12-17 Micron Technology, Inc. Laser ablative removal of photoresist
US6417090B1 (en) * 1999-01-04 2002-07-09 Advanced Micro Devices, Inc. Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer
US6255232B1 (en) 1999-02-11 2001-07-03 Taiwan Semiconductor Manufacturing Company Method for forming low dielectric constant spin-on-polymer (SOP) dielectric layer
US6114253A (en) * 1999-03-15 2000-09-05 Taiwan Semiconductor Manufacturing Company Via patterning for poly(arylene ether) used as an inter-metal dielectric
US6211063B1 (en) 1999-05-25 2001-04-03 Taiwan Semiconductor Manufacturing Company Method to fabricate self-aligned dual damascene structures
US20030205815A1 (en) * 1999-06-09 2003-11-06 Henry Chung Fabrication method of integrated circuits with borderless vias and low dielectric constant inter-metal dielectrics
JP2001007202A (ja) * 1999-06-22 2001-01-12 Sony Corp 半導体装置の製造方法
US6498399B2 (en) * 1999-09-08 2002-12-24 Alliedsignal Inc. Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits
JP3430091B2 (ja) 1999-12-01 2003-07-28 Ｎｅｃエレクトロニクス株式会社 エッチングマスク及びエッチングマスクを用いたコンタクトホールの形成方法並びにその方法で形成した半導体装置
US6432833B1 (en) 1999-12-20 2002-08-13 Micron Technology, Inc. Method of forming a self aligned contact opening
US6531389B1 (en) 1999-12-20 2003-03-11 Taiwan Semiconductor Manufacturing Company Method for forming incompletely landed via with attenuated contact resistance
AU2761301A (en) 2000-01-03 2001-07-16 Micron Technology, Inc. Method of forming a self-aligned contact opening
US6348706B1 (en) * 2000-03-20 2002-02-19 Micron Technology, Inc. Method to form etch and/or CMP stop layers
JP4149644B2 (ja) * 2000-08-11 2008-09-10 株式会社東芝 不揮発性半導体記憶装置
JP5350571B2 (ja) * 2000-08-21 2013-11-27 ダウ グローバル テクノロジーズ エルエルシー マイクロ電子デバイス製造に使用する有機ポリマー絶縁膜用ハードマスクとしての有機シリケート樹脂
US6617239B1 (en) 2000-08-31 2003-09-09 Micron Technology, Inc. Subtractive metallization structure and method of making
US7172960B2 (en) * 2000-12-27 2007-02-06 Intel Corporation Multi-layer film stack for extinction of substrate reflections during patterning
US6803314B2 (en) * 2001-04-30 2004-10-12 Chartered Semiconductor Manufacturing Ltd. Double-layered low dielectric constant dielectric dual damascene method
US6989108B2 (en) 2001-08-30 2006-01-24 Micron Technology, Inc. Etchant gas composition
US20030096090A1 (en) * 2001-10-22 2003-05-22 Boisvert Ronald Paul Etch-stop resins
KR100704469B1 (ko) * 2001-12-14 2007-04-09 주식회사 하이닉스반도체 반도체 소자 제조 방법
JP2004071705A (ja) * 2002-08-02 2004-03-04 Fujitsu Ltd 半導体装置及び半導体装置の製造方法
JP2004274020A (ja) * 2002-09-24 2004-09-30 Rohm & Haas Electronic Materials Llc 電子デバイス製造
KR100480636B1 (ko) * 2002-11-22 2005-03-31 삼성전자주식회사 반도체 장치의 제조방법
US7026650B2 (en) 2003-01-15 2006-04-11 Cree, Inc. Multiple floating guard ring edge termination for silicon carbide devices
US9515135B2 (en) * 2003-01-15 2016-12-06 Cree, Inc. Edge termination structures for silicon carbide devices
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JP5134193B2 (ja) * 2005-07-15 2013-01-30 株式会社東芝 半導体装置及びその製造方法
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100518988B1 (ko) * 1996-04-29 2005-12-01 텍사스 인스트루먼츠 인코포레이티드 집적회로절연체및그제조방법

Also Published As

Publication number Publication date
JPH0851154A (ja) 1996-02-20
DE69528409T2 (de) 2003-08-21
DE69528409D1 (de) 2002-11-07
EP0680084B1 (en) 2002-10-02
US5565384A (en) 1996-10-15
TW299484B (enExample) 1997-03-01
EP0680084A1 (en) 1995-11-02

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