KR950015652A - 반도체 집적회로장치의 제조방법 및 제조장치 - Google Patents

반도체 집적회로장치의 제조방법 및 제조장치 Download PDF

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Publication number
KR950015652A
KR950015652A KR1019940031084A KR19940031084A KR950015652A KR 950015652 A KR950015652 A KR 950015652A KR 1019940031084 A KR1019940031084 A KR 1019940031084A KR 19940031084 A KR19940031084 A KR 19940031084A KR 950015652 A KR950015652 A KR 950015652A
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KR
South Korea
Prior art keywords
hydrogen
semiconductor wafer
integrated circuit
manufacturing
chamber
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019940031084A
Other languages
English (en)
Korean (ko)
Inventor
히로미치 에나미
기요미 가츠야마
마사노리 가츠야마
Original Assignee
가나이 쓰토무
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쓰토무, 가부시키가이샤 히타치세이사쿠쇼 filed Critical 가나이 쓰토무
Publication of KR950015652A publication Critical patent/KR950015652A/ko
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67167—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H01L21/67213—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one ion or electron beam chamber

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
KR1019940031084A 1993-11-30 1994-11-24 반도체 집적회로장치의 제조방법 및 제조장치 Withdrawn KR950015652A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP93-300397 1993-11-30
JP5300397A JPH07153769A (ja) 1993-11-30 1993-11-30 半導体集積回路装置の製造方法および製造装置

Publications (1)

Publication Number Publication Date
KR950015652A true KR950015652A (ko) 1995-06-17

Family

ID=17884301

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940031084A Withdrawn KR950015652A (ko) 1993-11-30 1994-11-24 반도체 집적회로장치의 제조방법 및 제조장치

Country Status (5)

Country Link
US (1) US5543336A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH07153769A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR950015652A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CN (1) CN1107254A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW269738B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976919A (en) * 1994-06-10 1999-11-02 Matsushita Electric Industrial Co., Ltd. Apparatus and method of manufacturing semiconductor element
JP2978746B2 (ja) * 1995-10-31 1999-11-15 日本電気株式会社 半導体装置の製造方法
US6489219B1 (en) * 1995-11-09 2002-12-03 Micron Technology, Inc. Method of alloying a semiconductor device
JP3865145B2 (ja) * 1996-01-26 2007-01-10 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6222228B1 (en) * 1997-06-19 2001-04-24 Texas Instruments Incorporated Method for reducing gate oxide damage caused by charging
JP3998765B2 (ja) * 1997-09-04 2007-10-31 シャープ株式会社 多結晶半導体層の製造方法及び半導体装置の評価方法
US6165375A (en) 1997-09-23 2000-12-26 Cypress Semiconductor Corporation Plasma etching method
JP4174862B2 (ja) * 1998-08-04 2008-11-05 ソニー株式会社 薄膜トランジスタの製造方法および半導体装置の製造方法
CN100561687C (zh) * 2001-12-26 2009-11-18 东京毅力科创株式会社 衬底处理方法及半导体装置的制造方法
US6667243B1 (en) * 2002-08-16 2003-12-23 Advanced Micro Devices, Inc. Etch damage repair with thermal annealing
US9449831B2 (en) 2007-05-25 2016-09-20 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US20090179253A1 (en) 2007-05-25 2009-07-16 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8940645B2 (en) 2007-05-25 2015-01-27 Cypress Semiconductor Corporation Radical oxidation process for fabricating a nonvolatile charge trap memory device
US8633537B2 (en) 2007-05-25 2014-01-21 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
JP2009040394A (ja) * 2007-07-19 2009-02-26 Yamaha Motor Co Ltd 鞍乗型車両
US7659184B2 (en) * 2008-02-25 2010-02-09 Applied Materials, Inc. Plasma immersion ion implantation process with chamber seasoning and seasoning layer plasma discharging for wafer dechucking
US20130023097A1 (en) * 2011-07-14 2013-01-24 Purtell Robert J U-mos trench profile optimization and etch damage removal using microwaves
EP2831917A4 (en) * 2012-03-31 2015-11-04 Cypress Semiconductor Corp OXID NITRIDE OXIDE STACK WITH MULTIPLE OXYNITRIDE LAYERS
CN107346729A (zh) * 2016-05-04 2017-11-14 北大方正集团有限公司 半导体器件的基底及其制作方法和半导体器件
CN111034038B (zh) * 2017-09-29 2024-02-06 株式会社村田制作所 压电基板的制造装置和压电基板的制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3849204A (en) * 1973-06-29 1974-11-19 Ibm Process for the elimination of interface states in mios structures
JPS5352532A (en) * 1976-10-25 1978-05-13 Yoshizawa Sekkai Kogyo Kk Method of manufacturing raw materials for portland cement clinker
FR2461359A1 (fr) * 1979-07-06 1981-01-30 Commissariat Energie Atomique Procede et appareil d'hydrogenation de dispositifs a semi-conducteurs
JPS57118635A (en) * 1981-01-16 1982-07-23 Matsushita Electronics Corp Manufacture of semiconductor device
JPS58137218A (ja) * 1982-02-09 1983-08-15 Nec Corp シリコン単結晶基板の処理方法
JPS59143318A (ja) * 1983-02-03 1984-08-16 Seiko Epson Corp 光アニ−ル法
JPS6135525A (ja) * 1984-07-27 1986-02-20 Seiko Epson Corp 半導体装置の製造方法
JPH0770524B2 (ja) * 1987-08-19 1995-07-31 富士通株式会社 半導体装置の製造方法
EP0419693A1 (de) * 1989-09-25 1991-04-03 Siemens Aktiengesellschaft Verfahren zur Passivierung von Kristalldefekten in poly-kristallinem Silizium-Material
JP2668459B2 (ja) * 1991-03-14 1997-10-27 株式会社半導体エネルギー研究所 絶縁膜作製方法

Also Published As

Publication number Publication date
US5543336A (en) 1996-08-06
TW269738B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1996-02-01
CN1107254A (zh) 1995-08-23
JPH07153769A (ja) 1995-06-16

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19941124

PG1501 Laying open of application
PC1202 Submission of document of withdrawal before decision of registration

Comment text: [Withdrawal of Procedure relating to Patent, etc.] Withdrawal (Abandonment)

Patent event code: PC12021R01D

Patent event date: 19990903

WITB Written withdrawal of application