KR940016632A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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KR940016632A
KR940016632A KR1019930029252A KR930029252A KR940016632A KR 940016632 A KR940016632 A KR 940016632A KR 1019930029252 A KR1019930029252 A KR 1019930029252A KR 930029252 A KR930029252 A KR 930029252A KR 940016632 A KR940016632 A KR 940016632A
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lead
semiconductor device
surface side
reinforcing plate
semiconductor chip
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KR0147397B1 (ko
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마사오 고토
모리히코 이케미즈
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사토 후미오
가부시키가이샤 도시바
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    • H—ELECTRICITY
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L2224/45099—Material
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Abstract

본 발명은 다핀, 저열저항, 박형(薄型)의 반도체장치를 저가이면서 간단한 공정으로 제공하고자 하는 것이다.
본 발명에 있어서는, 캐리어 테이프(12)의 일면측에는 금속리드(11)가 부착되어 있다. 그리고, 금속리드(11)의 일단은 반도체칩(13)에 접속되어 있고, 금속리드(11)의 타단은 보강판(15)의 일면측에 부착된 리드 프레임(16)의 내부리드에 접속되어 있다. 또, 반도체칩(13)은 보강판(15)의 일면측에 탑재되어 있고, 내부리드의 선단은 보강판(15)의 개구부(18)에 위치하고 있다.

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 1실시예에 따른 반도체장치를 나타낸 사시도, 제 2 도는 제 1 도의 I-I' 선에 따른 단면도, 제 6 도는 제 1 도의 반도체장치의 변형예를 나타낸 단면도.

Claims (16)

  1. 캐리어 테이프(12)와, 이 캐리어 테이프(12)의 일면측에 부착되는 제 1 리드(11), 이 제 1 리드(11)의 일단에 접속되는 반도체칩(13) 및, 이 반도체칩(13)이 일면측에 탑재되는 보강판(15)을 구비한 것을 특징으로 하는 반도체장치.
  2. 제 1 항에 있어서, 상기 보강판(15)의 일측면에 부착되며 일단에 상기 제 1 리드(11)의 타단이 접속되는 제 2 리드(16)를 구비한 것을 특징으로 하는 반도체장치.
  3. 제 1 항 또는 제 2 항에 있어서, 상기 반도체칩(13)이 제 1 수지층(14)에 의해 피복되어 있는 것을 특징으로 하는 반도체장치.
  4. 제 2 항에 있어서, 상기 제 1 리드(11)가 상기 보강판(15)측으로 구부러지고, 상기 제 2 리드(16)가 상기 반도체칩(13)측으로 구부러져 있는 것을 특징으로 하는 반도체장치.
  5. 제 1 항에 있어서, 상기 캐리어 테이프(12)의 일면측과 상기 보강판(15)의 일면측이 서로 마주 보고있고, 상기 제 1 리드(11)가 상기 보강판(15)과는 반대측으로 구부러져 있는 것을 특징으로 하는 반도체장치.
  6. 제 2 항에 있어서, 상기 보강판(15)이 상기 제 2 리드(16)의 일단에 개구부(18)를 갖추고 있는 것을 특징으로 하는 반도체장치.
  7. 제 1 항 또는 제 2 항에 있어서, 상기 보강판(15)의 타면측에는 당해 반도체장치의 배치를 인식하기 위한 인식마크(17)가 설치되어 있는 것을 특징으로 하는 반도체장치.
  8. 제 1 항 또는 제 2 항에 있어서, 상기 보강판(15)이 열전도도가 큰 금속으로 구성되어 있는 것을 특징으로 하는 반도체장치.
  9. 제 1 항 또는 제 2 항에 있어서, 상기 보강판(15)의 타면측에는 방열핀(20)이 부착되어 있는 것을 특징으로 하는 반도체장치.
  10. 제 2 항에 있어서, 상기 보강판(15)의 일면측에는 당해 보강판과 동일한 크기의 보호틀(21)이 부착되어 있는 것을 특징으로 하는 반도체장치.
  11. 제 10 항에 있어서, 상기 보호틀(21)의 높이는, 상기 보강판(15)의 다른 쪽측의 면으로부터 상기 보호틀(21)의 윗면까지의 높이가 상기 보강판(15)의 다른 쪽측의 면으로부터 상기 반도체칩(13)을 피복하는 수지층(14)의 윗면까지의 높이와 같거나, 혹은 크게 되도록 설정되어 있는 것을 특징으로 하는 반도체장치.
  12. 제 2 항에 있어서, 상기 캐리어 테이프(12)의 타면측과 상기 보강판(15)의 일면측이 서로 마주 보고 있고, 적어도 상기 제 1 리드(11) 및, 상기 제 1 리드(11)와 상기 제 2 리드(16)의 접속부가 제 2 수지층(22)에 의해 피복되어 있는 것을 특징으로 하는 반도체장치.
  13. 제 2 항에 있어서, 상기 캐리어 테이프(12)의 일면측과 상기 보강판(15)의 일면측이 서로 마주 보고 있고, 적어도 상기 제 1 리드(11)와 상기 제 2 리드(16)의 접속부가 제 2 수지층(22)에 의해 피복되어 있는 것을 특징으로 하는 반도체장치.
  14. 제 1 항 또는 제 2 항에 있어서, 상기 보강판(15)의 타면측에는 당해 보강판과 일체로 이루는 복수의 돌기부가 형성되어 있는 것을 특징으로 하는 반도체장치.
  15. 캐리어 테이프(12)의 일면측에 형성되는 제 1 리드(11)의 일단과 반도체칩(13)을 접속하는 공정과, 개구부(18)를 갖춘 보강판(15)의 일면측에 제 2 리드(16)의 일단이 당해 개구부에 위치하도록 당해 제 2 리드를 부착하는 공정 및, 상기 개구부(18)를 매개해서 상기 제 1 리드(11)와 상기 제 2 리드(16)의 접속부에 열을 방출하기 위한스테이지를 맞추면서 열압착에 의해 상기 제1리드(11)의 타단과 상기 제 2 리드(16)의 일 단을 접속하는 공정을 구비하는 것을 특징으로 하는 반도체장치의 제조방법.
  16. 캐리어 테이프(12)의 일면측에 형성되는 제 1 리드(11)의 일단과 반도체칩(13)을 접속하는 공정과, 열압착에 의해 상기 제 1 리드(11)의 타단과 제 2 리드(16)의 일단을 접속하는 공정 및, 보강판(15)의 일면측에 상기 반도체칩(13) 및 상기 제 2 리드(16)를 부착하는 공정을 구비한 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930029252A 1992-12-28 1993-12-23 반도체장치 및 그 제조방법 Expired - Fee Related KR0147397B1 (ko)

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Application Number Priority Date Filing Date Title
JP4348663A JPH06204285A (ja) 1992-12-28 1992-12-28 半導体装置及びその製造方法
JP92-348663 1992-12-28

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KR0147397B1 KR0147397B1 (ko) 1998-11-02

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Cited By (1)

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KR101688079B1 (ko) * 2015-07-13 2016-12-20 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이의 제조 방법

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JP3238004B2 (ja) * 1993-07-29 2001-12-10 株式会社東芝 半導体装置の製造方法
JPH0831988A (ja) * 1994-07-20 1996-02-02 Nec Corp テープキャリアパッケージの封止構造
JP2798040B2 (ja) * 1996-02-21 1998-09-17 日本電気株式会社 半導体装置の製造方法
JP2924840B2 (ja) * 1997-02-13 1999-07-26 日本電気株式会社 Ｔａｐｅ−ＢＧＡタイプの半導体装置
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US5652184A (en) 1997-07-29
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