KR930020640A - 배선기판 조립체와 그 전기적 접합부 형성방법 - Google Patents
배선기판 조립체와 그 전기적 접합부 형성방법 Download PDFInfo
- Publication number
- KR930020640A KR930020640A KR1019930004249A KR930004249A KR930020640A KR 930020640 A KR930020640 A KR 930020640A KR 1019930004249 A KR1019930004249 A KR 1019930004249A KR 930004249 A KR930004249 A KR 930004249A KR 930020640 A KR930020640 A KR 930020640A
- Authority
- KR
- South Korea
- Prior art keywords
- metal
- insulating layer
- conductor pattern
- conductor
- stud
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 9
- 239000004020 conductor Substances 0.000 claims abstract 33
- 239000002184 metal Substances 0.000 claims abstract 25
- 229910052751 metal Inorganic materials 0.000 claims abstract 25
- 239000000758 substrate Substances 0.000 claims 6
- 238000004519 manufacturing process Methods 0.000 claims 3
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 239000000919 ceramic Substances 0.000 claims 1
- 238000005304 joining Methods 0.000 claims 1
- 238000005096 rolling process Methods 0.000 claims 1
- 230000008878 coupling Effects 0.000 abstract 2
- 238000010168 coupling process Methods 0.000 abstract 2
- 238000005859 coupling reaction Methods 0.000 abstract 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 abstract 1
- 229910052802 copper Inorganic materials 0.000 abstract 1
- 239000010949 copper Substances 0.000 abstract 1
- 229920001721 polyimide Polymers 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/50—Fixed connections
- H01R12/51—Fixed connections for rigid printed circuits or like structures
- H01R12/52—Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
- H01R12/523—Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures by an interconnection through aligned holes in the boards or multilayer board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0382—Continuously deformed conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10234—Metallic balls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10287—Metal wires as connectors or conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49151—Assembling terminal to base by deforming or shaping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
다층 배선 조립체는 보통 구리로된 배선패턴(4)과 교대로, 예를 들어 폴리이미드로된 절연층(3)의 적층(2)으로 구성된다. 회로패턴을 만들기 위해, 연속 배선패턴(4)이 금속 스터드 접합부(5)에 의해, 복수의 소정위치에서 사이에 놓인 절연층을 통해 서로에 접합된다.
스터드(5)는 절연층(3)의 드르홀을 통해 밑에 놓인 배선 패턴상에 스터드를 도선 결합하고, 다음에 도선 결합된 스터드의 도출 종단을 스탬핑하여 이것을 최상부 배선패턴(4)과 접촉하게 퍼지게 함으로써 적층의 조립 동안 형성된다. 예를들어 A
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 가층배선반 조립체의 단면도이다.
제2도는 스터드 마이크로범프(stud microbump)전기적 적합자의 스탬핑을 설명하는 도이다.
제3도는 스터드를 초기에 형성하는 배선접합 방법을 나타낸 도이다.
Claims (17)
- 절연층(3)의 일측의 제1전도체(4,13)가 상기 절연층(3)을 통해 연장되며 상기 제1전도체(4,13)위에 놓인 드루홀(31)을 통해, 상기 드루홀(31)을 통해, 상기 드루홀(31)을 통해 연장한 금속 접합부(5)에 의해, 상기 절연층(3)의 대향측에서 제2전도체(4)에 전기적으로 접속되어지는 배선기판 조립체 제작중 전기적 접합부를 만드는 방법에 있어서, 상기 금속접합부는, (a)상기 드루홀(31)을 통해 연장하도록 상기 제1전도체(4,13)상으로 금속스터드(5)를 결합시키고, (b)상기 금속 스터드(5)의 노출 종단(53)이 상기 제2전도체(4)와 원주 접촉하여 퍼지도록 그 종단을 평평하게 하는 것으로 형성되는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 금속 스터드(5)는 금속도선(64)의 종단을 상기 제1전도체(4,13)상으로 도선 결합하고 상기 도선 결합된 종단을 상기 금속도선(64)의 나머지에서 분리하여 형성되는 것을 특징으로 하는 방법.
- 제1항 또는 2항에 있어서, 열 및 초음파가 상기 금속스터드를 상기 제1전도체(4,13)상에 결합하도록 인가되는 것을 특징으로 하는 방법.
- 제1항 내지 3항중 어느 한 항에 있어서, 상기 금속 스터드(5)의 상기 노출 종단(53)은 스탬핑 또는 롤링에 의해 평평해지는 것을 특징으로 하는 방법.
- 제1항 내지 4항중 어느 한 항에 있어서, 상기 금속 스터드(5)의 노출 종단(53)의 평평한 부분을 상기 제2전도체(4)와 겹치는 외부 플랜지(54)를 형성하는 것을 특징으로 하는 방법.
- 내용없음.
- 제1도전체 패턴(4,13)을 형성하고; (i)절연층(3)을 상기 제1전도체 패턴(4,13)상에 중첩하고, 제2전도체패턴(4)은 상기 절연층(3) 위에 형성되며, 드루홀(31)은 상기 제1전도체 패턴위에 있는 복수의 소정 접합위치에서 상기 절연층(3)을 통해 형성되고; (ⅱ) 상기 복수의 소정위치에서 상기 제1및 제2전도체 패턴(4,13;4)사이를 전기적으로 접속하도록 상기 드루홀(3)에 금속 접합부(5)를 형성하는 것으로 이루어진 배선기판 조립체를 만드는 방법에 있어서, 상기 금속 접합부는, (a)상기 드루홀(31)의 상기 제1전도체 패턴(4,13)상으로 금속 스터드(5)를 결합시키고, (b)상기 결합된 스터드(5)를 스탬핑하여 상기 제2전도체 패턴(4)과 겹치게 접촉하여 이들 종단(53)을 외부 플랜지(54)안으로 평평하게 함으로써 형성되는 것을 특징으로 하는 방법.
- 제7항에 있어서, 상기 제1전도체 패턴은 조립체 기판(1)의 접합단자(13)로 구성되는 것을 특징으로 하는 방법.
- 제7항 또는 8항에 있어서, 상기 조립체를 다층 조립체(2)로 형성하기 위해 최소한 하나의 다른 절연층(4)이 다른 절연 패턴(4)을 가져, 상기 제2전도체 패턴에 관련하여 단계(ⅰ) 내지(ⅱ)를 반복하는 것을 이루어진 방법.
- 제7항 내지 9항중 어느 한 항에 있어서, 단계(a)에서 상기 금속 스터드(5)는 금속도선(64)의 종단을 상기 제1전도체 패턴(4,13)상에 결합시키고, 상기 결합된 종단(66)을 상기 도선(64)의 나머지에서 분리하여 상기 스터드(5′)를 형성하므로써 결합되는 것을 특징으로 하는 방법.
- 제7항 내지 10항중 어느 한 항에 있어서, 상기 금속스터드(5)는이하인 저항치를 갖는 것을 특징으로 하는 방법.
- 제1전도체 패턴(13,4), 상기 제1전도체 패턴상에 중접된 절연층(3) 그리고 상기 절연층(3)에 중첩된 다른 전도체 패턴(4)로 구성되고, 상기 전도체 패턴 사이의 금속 접합부는 상기 절연층의 드루홀(31)을 통해 연장한 배선기판 조립체에 있어서, 상기 금속 접합부는 상기 제1전도체 패턴상에 금속 결합된 제1종단과 다른 전도체 패턴(4)과 겹쳐 접촉한 평평한 외부 플랜지(54)를 갖는 제2종단(53)을 구비한 금속 스터드(5)인 것을 특징으로 하는 배선기판 조립체.
- 제12항에 있어서, 상기 제1전도체 패턴(13)은 상기 조립체의 굳은 기판(1)상에 있는 것을 특징으로 하는 배선기판 조립체.
- 제13항에 있어서, 상기 굳은 기판(1)은 세라믹 또는 Si로 되어 있는 것을 특징으로하는 배선기판 조립체.
- 제12항에 있어서, 상기 제1전도체 패턴은 이전의 절연층(3)상의 전도체 패턴(4)인 것을 특징으로 하는 배선기판 조립체.
- 제12항 내지 15항중 어느 한 항에 있어서, 상기 금속 스터드(5)는이하인 저항치를 갖는 것을 특징으로 하는 조립체.
- 기판(1) 그리고 각각 절연층(3)과 절연층(3)에 패턴된 배선층(4)으로 구성되는 결합층(2)의 기판에 중첩된 복수의 배선기판으로 구성되고, 연속한 상기 배선층(4)은 상기 절연층(3)을 통해 연장한 금속 접착부(5)에 의해 복수의 소정 위치에서 전기적으로 함께 접합되어 있는 다층 배선 조립체에 있어서, 상기 금속 접합부는이하인 저항치를 갖는 금속 스터드(5)로 형성되고, 각 상기 금속 스터드(5)는 열, 압력 및 초음파의 인가에 의해 상기 배선층(4)중 하나에 금속적으로 결합된 제1종단과 다른 배선층(14)과 중첩되어 접촉하여 외부 플랜지(54)를 구성하는 기계적으로 평평하게 퍼진 부분을 갖는 제2종단(53)을 구비하는 것을 특징으로 하는 다층배선 조립체.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP92-063146 | 1992-03-19 | ||
JP4063146A JP2748768B2 (ja) | 1992-03-19 | 1992-03-19 | 薄膜多層配線基板およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930020640A true KR930020640A (ko) | 1993-10-20 |
KR100272156B1 KR100272156B1 (ko) | 2000-12-01 |
Family
ID=13220820
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930004249A KR100272156B1 (ko) | 1992-03-19 | 1993-03-19 | 배선기판 조립체와 그 전기적 접합부 형성방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5497545A (ko) |
EP (1) | EP0561620B1 (ko) |
JP (1) | JP2748768B2 (ko) |
KR (1) | KR100272156B1 (ko) |
DE (1) | DE69325404T2 (ko) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5937515A (en) * | 1995-04-25 | 1999-08-17 | Johnson; Morgan T. | Reconfigurable circuit fabrication method |
US6252179B1 (en) * | 1995-04-27 | 2001-06-26 | International Business Machines Corporation | Electronic package on metal carrier |
US5914533A (en) * | 1995-06-06 | 1999-06-22 | International Business Machines Corporation | Multilayer module with thinfilm redistribution area |
JPH09116273A (ja) * | 1995-08-11 | 1997-05-02 | Shinko Electric Ind Co Ltd | 多層回路基板及びその製造方法 |
KR100186752B1 (ko) * | 1995-09-04 | 1999-04-15 | 황인길 | 반도체 칩 본딩방법 |
JP2820108B2 (ja) * | 1996-03-13 | 1998-11-05 | 日本電気株式会社 | 電子部品の実装構造およびその製造方法 |
US6045416A (en) * | 1996-04-02 | 2000-04-04 | Aries Electronics, Inc. | Universal production ball grid array socket |
US5730606A (en) * | 1996-04-02 | 1998-03-24 | Aries Electronics, Inc. | Universal production ball grid array socket |
TW406454B (en) | 1996-10-10 | 2000-09-21 | Berg Tech Inc | High density connector and method of manufacture |
US6310300B1 (en) * | 1996-11-08 | 2001-10-30 | International Business Machines Corporation | Fluorine-free barrier layer between conductor and insulator for degradation prevention |
US5853517A (en) * | 1996-11-08 | 1998-12-29 | W. L. Gore & Associates, Inc. | Method for coining solder balls on an electrical circuit package |
DE69730629T2 (de) * | 1996-12-26 | 2005-02-03 | Matsushita Electric Industrial Co., Ltd., Kadoma | Leiterplatte und Elektronikkomponente |
JPH1174651A (ja) | 1997-03-13 | 1999-03-16 | Ibiden Co Ltd | プリント配線板及びその製造方法 |
JPH11238831A (ja) * | 1997-12-16 | 1999-08-31 | Shinko Electric Ind Co Ltd | テープキャリア及びその製造方法 |
US6333565B1 (en) * | 1998-03-23 | 2001-12-25 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument |
JP3167296B2 (ja) * | 1998-07-31 | 2001-05-21 | 日本特殊陶業株式会社 | 樹脂製配線基板 |
US6449840B1 (en) * | 1998-09-29 | 2002-09-17 | Delphi Technologies, Inc. | Column grid array for flip-chip devices |
US6376352B1 (en) * | 1998-11-05 | 2002-04-23 | Texas Instruments Incorporated | Stud-cone bump for probe tips used in known good die carriers |
US6163957A (en) * | 1998-11-13 | 2000-12-26 | Fujitsu Limited | Multilayer laminated substrates with high density interconnects and methods of making the same |
US6354850B1 (en) * | 1998-12-15 | 2002-03-12 | Fci Americas Technology, Inc. | Electrical connector with feature for limiting the effects of coefficient of thermal expansion differential |
US6259039B1 (en) * | 1998-12-29 | 2001-07-10 | Intel Corporation | Surface mount connector with pins in vias |
US6164993A (en) * | 1999-02-12 | 2000-12-26 | Micron Technology, Inc. | Zero insertion force sockets using negative thermal expansion materials |
US20020076917A1 (en) * | 1999-12-20 | 2002-06-20 | Edward P Barth | Dual damascene interconnect structure using low stress flourosilicate insulator with copper conductors |
DE10035175C1 (de) * | 2000-07-19 | 2002-01-03 | Fraunhofer Ges Forschung | Verfahren zur Herstellung einer elektrischen und/oder mechanischen Verbindung von flexiblen Dünnfilmsubstraten |
WO2002085380A1 (en) * | 2001-04-18 | 2002-10-31 | Geltex Pharmaceuticals, Inc. | Method for treating gout and reducing serum uric acid |
DE10125497C2 (de) | 2001-05-23 | 2003-06-05 | Pac Tech Gmbh | Verfahren zur Herstellung eines Kontaktsubstrats sowie Kontaktsubstrat |
US7189595B2 (en) * | 2001-05-31 | 2007-03-13 | International Business Machines Corporation | Method of manufacture of silicon based package and devices manufactured thereby |
US6878608B2 (en) * | 2001-05-31 | 2005-04-12 | International Business Machines Corporation | Method of manufacture of silicon based package |
EP1395100B1 (de) * | 2002-08-29 | 2011-06-15 | Asetronics AG | Verfahren zur Bearbeitung und Herstellung von Leiterplatten sowie Leiterplatte |
JP4308716B2 (ja) | 2004-06-09 | 2009-08-05 | 新光電気工業株式会社 | 半導体パッケージの製造方法 |
DE102005020087A1 (de) * | 2005-04-29 | 2006-11-09 | Infineon Technologies Ag | Verfahren und Vorrichtung zur Erzeugung von einem bondbaren Flächenbereich auf einem Träger |
JP4503578B2 (ja) * | 2006-11-13 | 2010-07-14 | 大日本印刷株式会社 | プリント配線板 |
US8716867B2 (en) * | 2010-05-12 | 2014-05-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming interconnect structures using pre-ink-printed sheets |
US10381322B1 (en) | 2018-04-23 | 2019-08-13 | Sandisk Technologies Llc | Three-dimensional memory device containing self-aligned interlocking bonded structure and method of making the same |
US10879260B2 (en) | 2019-02-28 | 2020-12-29 | Sandisk Technologies Llc | Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3103547A (en) * | 1963-09-10 | ansley | ||
US2990533A (en) * | 1958-04-09 | 1961-06-27 | Stokes D Hughes | Terminal post for circuit board |
US3201851A (en) * | 1960-10-05 | 1965-08-24 | Sanders Associates Inc | Method of making interconnecting multilayer circuits |
US3281923A (en) * | 1964-08-27 | 1966-11-01 | Corning Glass Works | Method of attaching leads to thin films |
US3445929A (en) * | 1966-08-03 | 1969-05-27 | Nicholas L Wolf | Method of connecting a terminal to a printed circuit panel |
US3446908A (en) * | 1966-11-01 | 1969-05-27 | Sanders Associates Inc | Printed circuit terminations and methods of making the same |
GB1260468A (en) * | 1968-03-28 | 1972-01-19 | Nat Res Dev | Improvements in or relating to the formation of connections on microelectronic circuits |
FR2137227B2 (ko) * | 1971-05-17 | 1973-11-30 | Vayda Pierre Andre | |
US3926360A (en) * | 1974-05-28 | 1975-12-16 | Burroughs Corp | Method of attaching a flexible printed circuit board to a rigid printed circuit board |
JPS5824037B2 (ja) * | 1980-05-26 | 1983-05-18 | 富士通株式会社 | 導体ボ−ル配列方法 |
JPS59208751A (ja) * | 1983-05-13 | 1984-11-27 | Hitachi Ltd | バンプ形成方法 |
JPS6129080A (ja) * | 1984-07-19 | 1986-02-08 | アルプス電気株式会社 | フイルム被覆端子およびその製造法 |
US4727633A (en) * | 1985-08-08 | 1988-03-01 | Tektronix, Inc. | Method of securing metallic members together |
US4771537A (en) * | 1985-12-20 | 1988-09-20 | Olin Corporation | Method of joining metallic components |
US4881906A (en) * | 1988-02-25 | 1989-11-21 | Helwett-Packard Company | Method for obtaining electrical interconnect using a solderable mechanical fastener |
JPH02148878A (ja) * | 1988-11-30 | 1990-06-07 | Toshiba Lighting & Technol Corp | スルホール端子 |
US5024372A (en) * | 1989-01-03 | 1991-06-18 | Motorola, Inc. | Method of making high density solder bumps and a substrate socket for high density solder bumps |
-
1992
- 1992-03-19 JP JP4063146A patent/JP2748768B2/ja not_active Expired - Fee Related
-
1993
- 1993-03-17 DE DE69325404T patent/DE69325404T2/de not_active Expired - Fee Related
- 1993-03-17 EP EP93302005A patent/EP0561620B1/en not_active Expired - Lifetime
- 1993-03-18 US US08/034,372 patent/US5497545A/en not_active Expired - Fee Related
- 1993-03-19 KR KR1019930004249A patent/KR100272156B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69325404D1 (de) | 1999-07-29 |
KR100272156B1 (ko) | 2000-12-01 |
EP0561620A3 (ko) | 1994-04-06 |
DE69325404T2 (de) | 2000-03-02 |
US5497545A (en) | 1996-03-12 |
JP2748768B2 (ja) | 1998-05-13 |
JPH05267402A (ja) | 1993-10-15 |
EP0561620B1 (en) | 1999-06-23 |
EP0561620A2 (en) | 1993-09-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR930020640A (ko) | 배선기판 조립체와 그 전기적 접합부 형성방법 | |
US5770476A (en) | Passive interposer including at least one passive electronic component | |
JPH0697225A (ja) | 半導体装置 | |
US3977074A (en) | Double sided printed circuit board and method for making same | |
US4164071A (en) | Method of forming a circuit board with integral terminals | |
JP2000165034A (ja) | フレキシブルプリント配線板及びその接続方法 | |
JPH0582917A (ja) | フレキシブル配線板 | |
JPH02239695A (ja) | 多層プリント配線板 | |
JPH06224587A (ja) | シ−ルド層を有する可撓性回路基板 | |
JPS5930555Y2 (ja) | プリント基板 | |
US20030209732A1 (en) | Apparatus for routing signals | |
JP2961859B2 (ja) | 多層セラミック基板 | |
JPS5911458Y2 (ja) | 印刷配線板 | |
JPH07106727A (ja) | フレキシブル印刷配線板の接続構造 | |
JPS6149499A (ja) | フレキシブル多層配線基板 | |
JPH0343724Y2 (ko) | ||
US6518672B2 (en) | Multi-layer wiring board substrate and semiconductor device using the multi-layer wiring substrate | |
JP3141682B2 (ja) | 複合リードフレーム | |
JPH10150246A (ja) | プリント配線基板 | |
JPH08264914A (ja) | 加熱圧着接続型バンプ付きfpc | |
JP2668558B2 (ja) | 積層基板 | |
JPH02158194A (ja) | 多層セラミック回路基板 | |
JPH0595174A (ja) | フレキシブルプリント配線板 | |
JPS6348156B2 (ko) | ||
JPS6185842A (ja) | 交差配線方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20030801 Year of fee payment: 4 |
|
LAPS | Lapse due to unpaid annual fee |