JPS5824037B2 - 導体ボ−ル配列方法 - Google Patents

導体ボ−ル配列方法

Info

Publication number
JPS5824037B2
JPS5824037B2 JP55069818A JP6981880A JPS5824037B2 JP S5824037 B2 JPS5824037 B2 JP S5824037B2 JP 55069818 A JP55069818 A JP 55069818A JP 6981880 A JP6981880 A JP 6981880A JP S5824037 B2 JPS5824037 B2 JP S5824037B2
Authority
JP
Japan
Prior art keywords
conductor
green sheet
balls
mask
pressurized air
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55069818A
Other languages
English (en)
Other versions
JPS56165398A (en
Inventor
横山博三
横内貴志男
亀原伸男
小川弘美
村川恭平
丹羽紘一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55069818A priority Critical patent/JPS5824037B2/ja
Priority to KR1019810001124A priority patent/KR840002470B1/ko
Priority to DE8181301493T priority patent/DE3171778D1/de
Priority to EP81301493A priority patent/EP0040905B1/en
Priority to US06/252,214 priority patent/US4346516A/en
Publication of JPS56165398A publication Critical patent/JPS56165398A/ja
Publication of JPS5824037B2 publication Critical patent/JPS5824037B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11005—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bump connector, e.g. marks, spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0382—Continuously deformed conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10234—Metallic balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49151—Assembling terminal to base by deforming or shaping
    • Y10T29/49153—Assembling terminal to base by deforming or shaping with shaping or forcing terminal into base aperture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49636—Process for making bearing or component thereof
    • Y10T29/49643—Rotary bearing
    • Y10T29/49679—Anti-friction bearing or component thereof
    • Y10T29/49694—Ball making

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Devices For Post-Treatments, Processing, Supply, Discharge, And Other Processes (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 本発明はセラミック多層基板のバイアホール作製のため
の導体ボールの充填に係り、特に空気による加圧を用い
てボール配列用マスクとグリーンシートを密着させて導
体ボールを配列する方法に関する。
最近半導体素子の高密度化に伴い、これら素子を搭載す
る回路基板よりも配線密度の高いものが要求され、その
ため導体回路の線幅の微細化と多層化がはかられている
。
この多層化されたセラミック基板のバイアホールを形成
する場合、例えば第１図に示すように金型１上にグリー
ンシート２をのせ、そのグリーンシート２上にメタルマ
スク３を用いて導体ボール４を配列し、押し込み治具５
により加圧され、グリーンシート２内に導体ボール４を
充填している。
なお６はガイドピンである。
上記メタルマスク３はステンレス材よりなりバイアホー
ルパターンに合せた位置に導体ボール４の入る孔があけ
られていて、読札にバイアホール形成用の導体ボール４
を配列する。
メタルマスク３の厚さが第２図イのように薄すぎると、
導体ボール４はメタルマスク３の孔にガイドされずに外
れ、又第２図口のように厚すぎると、導体ボール４がメ
タルマスク３の孔に２個以上入り不都合である。
そのため、メタルマスク３の厚さは導体ボール４の径と
同程度であることが要求されている。
ところが導体ボール４の径は、例えば８０μｍというよ
うに小さいため、この導体ボールの配列に使われるメタ
ルマスク３は薄くなり、容易に変形を起し、本来密着す
べきメタルマスク３とグリーンシート２の間に隙間が生
じ、導体ボール４は第３図の点線で示すようにメタルマ
スク３の孔に正確にガイドされず、グリーンシート２上
の所定位置に充填されない問題があった。
本発明の目的はボール配列用マスクにグリーンシートを
加圧空気で押着することにより、該マスク上に導体ボー
ルを確実に配列させることにより上述の問題を改善する
にある。
本発明の特徴は金型に加圧空気を噴出する孔を設け、読
札よりの加圧空気によりグリーンシートをマスクに対し
密着させた後、導体ボールを配列して上述の目的を達し
ている。
以下、本発明について実施例を用いて説明する。
第４図は本発明による導体ボール配列方法の１実施例を
説明するための装置の断面図である。
図において、７は金型、８は加圧空気を噴出する孔、９
はグリーンシート、１０はメタルマスク、１１は導体ボ
ール、１２はガイドピン、１３は凸起、１４は治具、１
５は加圧空気である。
金型７に加圧空気を噴出することのできる孔、を設けて
いる、金型７に設けられたガイドピン１２に挿入される
孔を有するグリーンシート９を金型７上にのせ、その上
にボール配列用メタルマスク１０を重ねる。
グリーンシート９は柔らかいので、大きな加圧空気を用
いなくとも変形するので、メタルマスク１０に対してグ
リーンシート９が密着し隙間を生じない比較的大きな圧
力をもつ空気１５を金型７の噴出孔８より噴出するだけ
でよい。
メタルマスク１０はバイアホールパターンに合わせて導
体ボール１１が入る孔が設けられているので、導体ボー
ル１１はメタルマスク１０の孔に確実にガイドされて、
グリーンシート９上の所定位置に正確に配置される。
以上のように導体ボール配列用メタルマスク１０に対し
、セラミックのグリーンシート９を下方から加圧空気で
押着することにより、メタルマスク１０とグリーンシー
トの間に隙間を生じることが解消され、従って該隙間か
ら導体ボール１１が逃げたり、或いは位置ずれを生じた
りしない。
従って治具１４の凸起１３で導体ボール１１を押圧（約
１ ｋｙ／ ｃｒＡ ）すれば、導体ボール１１はグリ
ーンシート９上でマスク１０と完全に一致した位置で充
填される。
最近のように一層に数千のバイアホールを有するような
多層回路基板の形成において、本発明のような簡単な方
法でグリーンシート上の正確な位置にバイアホールが形
成できるので、上下回路間の導通の信頼性を著しく向上
できる。
以上実施例により本発明を説明したが、本発明によれば
金型に加圧空気を噴出する孔を設け、読札よりの加圧空
気によりグリーンシートをマスクに対し密着させた後、
導体ボールを配列することにより、ボールの充填位置が
マスクと完全に一致し、多層基板のバイアホールの信頼
性を著しく向上できる効果は大きい。
【図面の簡単な説明】
第１図イ、口は従来のバイアホール形成のための導体ボ
ール充填装置を説明するための断面図、第２図イ、口、
第３図は従来の導体ボールの配列を説明するための断面
図、第４図は本発明による導体ボール充填装置のボール
の配列状態を説明するための断面図。 図中、７は金型、８は加圧空気を噴出する孔、９はグリ
ーンシート、１０はメタルマスク、１１は導体ボール、
１２はガイドピン、１３は凸起、１４は治具、１５は加
圧空気である。

Claims (1)

    【特許請求の範囲】
  1. １ 金型に載せたグリーンシート上に、バイアホールパ
    ターンに合ったボール配列用マスクを載せ、該マスクに
    導体ボールを配列し、該導体ボールを押し込み治具によ
    りグリーンシートに充填しバイアホールを形成するにお
    いて、前記金型に加圧空気を噴出する孔を設け、読札よ
    りの加圧空気により前記グリーンシートを前記マスクに
    対し密着させた後、導体ボールを配列することを特徴と
    する導体ボール配列方法。
JP55069818A 1980-05-26 1980-05-26 導体ボ−ル配列方法 Expired JPS5824037B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP55069818A JPS5824037B2 (ja) 1980-05-26 1980-05-26 導体ボ−ル配列方法
KR1019810001124A KR840002470B1 (ko) 1980-05-26 1981-04-03 요업체회로기판(窯業體回路基板) 제조방법
DE8181301493T DE3171778D1 (en) 1980-05-26 1981-04-07 The manufacture of ceramic circuit substrates
EP81301493A EP0040905B1 (en) 1980-05-26 1981-04-07 The manufacture of ceramic circuit substrates
US06/252,214 US4346516A (en) 1980-05-26 1981-04-08 Method of forming a ceramic circuit substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55069818A JPS5824037B2 (ja) 1980-05-26 1980-05-26 導体ボ−ル配列方法

Publications (2)

Publication Number Publication Date
JPS56165398A JPS56165398A (en) 1981-12-18
JPS5824037B2 true JPS5824037B2 (ja) 1983-05-18

Family

ID=13413714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55069818A Expired JPS5824037B2 (ja) 1980-05-26 1980-05-26 導体ボ−ル配列方法

Country Status (5)

Country Link
US (1) US4346516A (ja)
EP (1) EP0040905B1 (ja)
JP (1) JPS5824037B2 (ja)
KR (1) KR840002470B1 (ja)
DE (1) DE3171778D1 (ja)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4412642A (en) * 1982-03-15 1983-11-01 Western Electric Co., Inc. Cast solder leads for leadless semiconductor circuits
JPS59995A (ja) * 1982-06-16 1984-01-06 富士通株式会社 銅導体多層構造体の製造方法
US4943334A (en) * 1986-09-15 1990-07-24 Compositech Ltd. Method for making reinforced plastic laminates for use in the production of circuit boards
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KR830005720A (ko) 1983-09-09
DE3171778D1 (en) 1985-09-19
EP0040905B1 (en) 1985-08-14
JPS56165398A (en) 1981-12-18
EP0040905A1 (en) 1981-12-02
US4346516A (en) 1982-08-31
KR840002470B1 (ko) 1984-12-29

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