KR920017246A - 반도체 집적 회로 장치 - Google Patents
반도체 집적 회로 장치 Download PDFInfo
- Publication number
- KR920017246A KR920017246A KR1019920001650A KR920001650A KR920017246A KR 920017246 A KR920017246 A KR 920017246A KR 1019920001650 A KR1019920001650 A KR 1019920001650A KR 920001650 A KR920001650 A KR 920001650A KR 920017246 A KR920017246 A KR 920017246A
- Authority
- KR
- South Korea
- Prior art keywords
- integrated circuit
- semiconductor integrated
- circuit device
- region
- scale cell
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title description 3
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 한 실시예에 따른 반도체 집적 회로 장치의 구성을 개략적으로 도시한 블록도, 제2도는 반도체 집적 회로 장치에 있어서 스루 배선을 통해 전달되는 신호의 진폭 변화를 도시한 설명도.
Claims (1)
- 대규모 셀(1), 상기 대규모 셀이 형성되어 있는 제1영역을 통과하는 스루 배선(15), 상기 대규모 셀이 형성되어 있지 않은 제2영역과 상기 제1영역과의 경계 부분에 상기 스루 배선의 일단이 접속되어 상기 제2영역에서 전달되어 온 신호의 레벨을 낮게 변환시켜 상기 제1영역으로 전달하는 입력 버퍼 회로(11) 및 상기 경계 부분에 상기 스루 배선의 타단이 접속되어 상기 제1영역에서 전달되어 온 신호의 레벨을 높게 변환시켜 상기 제2영역으로 전달시키는 출력 버퍼 회로(12)를 포함하는 것을 특징으로 하는 반도체 집적 회로 장치.※참고사항:최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP91-13514 | 1991-02-04 | ||
JP3013514A JP2645183B2 (ja) | 1991-02-04 | 1991-02-04 | 半導体集積回路装置 |
JP91-013514 | 1991-02-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920017246A true KR920017246A (ko) | 1992-09-26 |
KR960000717B1 KR960000717B1 (ko) | 1996-01-11 |
Family
ID=11835260
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920001650A KR960000717B1 (ko) | 1991-02-04 | 1992-02-01 | 반도체 집적회로 장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5311074A (ko) |
JP (1) | JP2645183B2 (ko) |
KR (1) | KR960000717B1 (ko) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05326835A (ja) * | 1992-05-15 | 1993-12-10 | Nec Corp | 半導体集積回路装置 |
US6204683B1 (en) | 1999-05-18 | 2001-03-20 | Intel Corporation | Apparatus and method for reducing crosstalk in an integrated circuit which includes a signal bus |
JP4683762B2 (ja) * | 2001-05-10 | 2011-05-18 | ルネサスエレクトロニクス株式会社 | 半導体装置設計方法、半導体装置設計用プログラム、半導体装置設計装置 |
JP4498787B2 (ja) * | 2003-04-30 | 2010-07-07 | パナソニック株式会社 | 半導体装置 |
JP4770285B2 (ja) * | 2005-06-20 | 2011-09-14 | 富士ゼロックス株式会社 | 画像処理装置及びその制御プログラム |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR910008521B1 (ko) * | 1983-01-31 | 1991-10-18 | 가부시기가이샤 히다찌세이사꾸쇼 | 반도체집적회로 |
JPS62202537A (ja) * | 1986-02-19 | 1987-09-07 | Hitachi Ltd | 半導体集積回路装置 |
US4931672A (en) * | 1987-11-20 | 1990-06-05 | Tandem Computers Incorporated | True TTL to true ECL bi-directional tristatable translator driver circuit |
KR910008099B1 (ko) * | 1988-07-21 | 1991-10-07 | 삼성반도체통신주식회사 | 메모리 칩의 파워 및 시그널라인 버싱방법 |
US5084637A (en) * | 1989-05-30 | 1992-01-28 | International Business Machines Corp. | Bidirectional level shifting interface circuit |
US4973863A (en) * | 1989-12-28 | 1990-11-27 | Eastman Kodak Company | TTL-ECL interface circuit |
JP2982196B2 (ja) * | 1990-02-06 | 1999-11-22 | 日本電気株式会社 | 異電源インターフェース回路 |
US5023488A (en) * | 1990-03-30 | 1991-06-11 | Xerox Corporation | Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines |
-
1991
- 1991-02-04 JP JP3013514A patent/JP2645183B2/ja not_active Expired - Fee Related
-
1992
- 1992-02-01 KR KR1019920001650A patent/KR960000717B1/ko not_active IP Right Cessation
- 1992-02-03 US US07/829,373 patent/US5311074A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5311074A (en) | 1994-05-10 |
JPH04247651A (ja) | 1992-09-03 |
KR960000717B1 (ko) | 1996-01-11 |
JP2645183B2 (ja) | 1997-08-25 |
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