KR890011209A - 듀일 슬로프 파형 발생회로 - Google Patents

듀일 슬로프 파형 발생회로 Download PDF

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Publication number
KR890011209A
KR890011209A KR870014053A KR870014053A KR890011209A KR 890011209 A KR890011209 A KR 890011209A KR 870014053 A KR870014053 A KR 870014053A KR 870014053 A KR870014053 A KR 870014053A KR 890011209 A KR890011209 A KR 890011209A
Authority
KR
South Korea
Prior art keywords
slope
input signal
slope waveform
waveform generator
generator
Prior art date
Application number
KR870014053A
Other languages
English (en)
Other versions
KR900008436B1 (ko
Inventor
정형섭
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870014053A priority Critical patent/KR900008436B1/ko
Priority to US07/247,048 priority patent/US4894560A/en
Priority to GB8822742A priority patent/GB2213668B/en
Priority to NL8802390A priority patent/NL193335C/nl
Priority to JP63251010A priority patent/JPH0775317B2/ja
Priority to FR8813175A priority patent/FR2624328B1/fr
Publication of KR890011209A publication Critical patent/KR890011209A/ko
Application granted granted Critical
Publication of KR900008436B1 publication Critical patent/KR900008436B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/02—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

내용 없음

Description

듀일 슬로프 파형 발생회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 회로도.
A: 제1 슬로프 발생부, B: 제2 슬로프 발생부, M1-M6: MOS 트랜지스터.

Claims (2)

  1. 제2슬로프 발생부(B)의 각 게이트 측에 출력신호(OUT)와 제 1슬로프 발생부(A)를 통한 입력신호(IN)가 인가되게 접속하고, 풀잎.다운 MOS 트랜지스터(M3,M6)의 각 게이트측에 입력신호(IN)와 제2 슬로프 발생부(B)를 통한 입력신호(IN)가 인가되게 접속 구성함을 특징으로 하는 듀얼 슬로프 파형발생회로.
  2. 제1항에 있어서, 제1 슬로프 발생부(A)를 N.PMOS 트랜지스터(M2,M1)로 된 인버터 회로로 구성하고, 제 2슬로프 발생부 (B)를 N.PMOS 트랜지스터(M3M4)를 병렬 접속하여 구성함을 특징으로 하는 듀얼 슬로프 파형 발행회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870014053A 1987-12-08 1987-12-08 듀얼 슬로프 파형 발생회로 KR900008436B1 (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019870014053A KR900008436B1 (ko) 1987-12-08 1987-12-08 듀얼 슬로프 파형 발생회로
US07/247,048 US4894560A (en) 1987-12-08 1988-09-16 Dual-slope waveform generation circuit
GB8822742A GB2213668B (en) 1987-12-08 1988-09-28 A dual-slope waveform generation circuit
NL8802390A NL193335C (nl) 1987-12-08 1988-09-29 Inrichting voor het opwekken van een golfvorm met tweevoudige helling.
JP63251010A JPH0775317B2 (ja) 1987-12-08 1988-10-06 デュアルスロープ波形発生回路
FR8813175A FR2624328B1 (fr) 1987-12-08 1988-10-07 Circuit generateur de forme d'onde a double pente, notamment pour circuit de pilotage d'amplificateur de detection de memoire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870014053A KR900008436B1 (ko) 1987-12-08 1987-12-08 듀얼 슬로프 파형 발생회로

Publications (2)

Publication Number Publication Date
KR890011209A true KR890011209A (ko) 1989-08-14
KR900008436B1 KR900008436B1 (ko) 1990-11-20

Family

ID=19266795

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870014053A KR900008436B1 (ko) 1987-12-08 1987-12-08 듀얼 슬로프 파형 발생회로

Country Status (6)

Country Link
US (1) US4894560A (ko)
JP (1) JPH0775317B2 (ko)
KR (1) KR900008436B1 (ko)
FR (1) FR2624328B1 (ko)
GB (1) GB2213668B (ko)
NL (1) NL193335C (ko)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5004936A (en) * 1989-03-31 1991-04-02 Texas Instruments Incorporated Non-loading output driver circuit
US4958093A (en) * 1989-05-25 1990-09-18 International Business Machines Corporation Voltage clamping circuits with high current capability
US5121013A (en) * 1990-02-12 1992-06-09 Advanced Micro Devices, Inc. Noise reducing output buffer circuit with feedback path
KR920010346B1 (ko) * 1990-05-23 1992-11-27 삼성전자 주식회사 반도체 메모리의 센스앰프 구동회로
US5241221A (en) * 1990-07-06 1993-08-31 North American Philips Corp., Signetics Div. CMOS driver circuit having reduced switching noise
US5319252A (en) * 1992-11-05 1994-06-07 Xilinx, Inc. Load programmable output buffer
US5448181A (en) * 1992-11-06 1995-09-05 Xilinx, Inc. Output buffer circuit having reduced switching noise
JP3194636B2 (ja) * 1993-01-12 2001-07-30 三菱電機株式会社 レベル変換回路、レベル変換回路を内蔵したエミュレータ用マイクロコンピュータ、レベル変換回路を内蔵したピギーバックマイクロコンピュータ、レベル変換回路を内蔵したエミュレートシステム及びレベル変換回路を内蔵したｌｓｉテストシステム
US5481500A (en) * 1994-07-22 1996-01-02 International Business Machines Corporation Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories
JP3442149B2 (ja) * 1994-07-28 2003-09-02 富士通株式会社 半導体回路
FR2847354B1 (fr) * 2002-11-18 2005-01-28 Atmel Nantes Sa Circuit tampon de sortie a commande en tension differee, et composant integre correspondant
JP4015937B2 (ja) * 2002-12-06 2007-11-28 松下電器産業株式会社 デューティ比補正回路
US9162255B1 (en) * 2010-01-13 2015-10-20 Fujifilm Sonosite, Inc. Tunable ultrasound transmitter
US8188773B1 (en) * 2011-03-29 2012-05-29 King Fahd University Of Petroleum & Minerals Voltage-controlled dual-slope square and triangular waveform generator
US9467143B1 (en) * 2015-09-24 2016-10-11 Qualcomm Incorporated Inversely proportional voltage-delay buffers for buffering data according to data voltage levels
DE102021111796A1 (de) * 2021-03-19 2022-09-22 Infineon Technologies Ag Hochgeschwindigkeitsdigitalsignaltreiber mit niedrigem leistungsverbrauch

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58116759A (ja) * 1981-12-29 1983-07-12 Fujitsu Ltd 出力ドライバ回路
JPS5974721A (ja) * 1982-10-21 1984-04-27 Toshiba Corp シユミツト・トリガ回路
JPH07107978B2 (ja) * 1985-11-07 1995-11-15 ロ−ム株式会社 Ｃ−ｍｏｓ回路

Also Published As

Publication number Publication date
GB2213668B (en) 1991-11-27
NL8802390A (nl) 1989-07-03
JPH01174010A (ja) 1989-07-10
FR2624328A1 (fr) 1989-06-09
JPH0775317B2 (ja) 1995-08-09
GB2213668A (en) 1989-08-16
GB8822742D0 (en) 1988-11-02
NL193335B (nl) 1999-02-01
KR900008436B1 (ko) 1990-11-20
FR2624328B1 (fr) 1992-10-30
NL193335C (nl) 1999-06-02
US4894560A (en) 1990-01-16

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