KR920015474A - 드라이 에칭 방법 - Google Patents

드라이 에칭 방법 Download PDF

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Publication number
KR920015474A
KR920015474A KR1019920001062A KR920001062A KR920015474A KR 920015474 A KR920015474 A KR 920015474A KR 1019920001062 A KR1019920001062 A KR 1019920001062A KR 920001062 A KR920001062 A KR 920001062A KR 920015474 A KR920015474 A KR 920015474A
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South Korea
Prior art keywords
based material
dry etching
sulfur
etching method
substrate
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KR1019920001062A
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English (en)
Inventor
신고 가도무라
마사가즈 무로야마
Original Assignee
오가 노리오
소니 가부시기가이샤
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Publication of KR920015474A publication Critical patent/KR920015474A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음

Description

드라이 에칭 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원의 제1의 발명을 콘택트홀가공에 적용한 일예에 있어서, 에칭전의 웨이퍼상태를 나타낸 개략단면도, 제2도는 전술한 제1도에 도시된 상태에 있어서, 콘택트홀의 형성의 도중상태에 있어서 트렌칭이 발생한 상태를 나타낸 개략단면도, 제3도는 전술한 제2도에 도시된 상태에 있어서, 절입부에 S가 퇴적한 상태를 나타낸 개략단면도.

Claims (2)

  1. S2F2,SF2, SF4, S2F10, S3Cl2, S2Cl2, SCl2에서 선정되는 어느 1종의 가스를 함유하는 에칭가스를 사용하여, 표면요부(凹部)와 표면철부(凸部)를 가진 실리콘계 재료 또는 산화실리콘계 재료로 이루어지는 피처리기판을 0℃이하로 냉각하면서, 최소한 상기 표면요부에 황을 퇴적시키는 과정과, 상기 표면철부와 퇴적한 상기 황을 동시에 제거하는 과정을 경합(競合)시킬 수 있는 조건으로 상기 피처리기판을 에칭하는 것을 특징으로 하는 드리이 에칭 방법.
  2. S2F2,SF2, SF4, S2F10, S3Cl2, S2Cl2, SCl2에서 선정되는 어느 1종의 가스를 함유하는 에칭가스를 사용하여, 표면요부와 표면철부를 가진 실리콘계 재료 또는 산화실리콘계 재료로 이루어지는 피처리기판을 0℃이하로 냉각하면서, 상기 표면요부에 황을 퇴적시키는 공정과, 상기 표면철부와 퇴적한 상기 황을 동시에 제거하는 공정을 가진 것을 특징으로 하는 드라이 에칭 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920001062A 1991-01-25 1992-01-25 드라이 에칭 방법 KR920015474A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP91-25568 1991-01-25
JP3025568A JP3018517B2 (ja) 1991-01-25 1991-01-25 ドライエッチング方法

Publications (1)

Publication Number Publication Date
KR920015474A true KR920015474A (ko) 1992-08-26

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920001062A KR920015474A (ko) 1991-01-25 1992-01-25 드라이 에칭 방법

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US (1) US5320708A (ko)
JP (1) JP3018517B2 (ko)
KR (1) KR920015474A (ko)

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US5702567A (en) * 1995-06-01 1997-12-30 Kabushiki Kaisha Toshiba Plurality of photolithographic alignment marks with shape, size and spacing based on circuit pattern features
US6979632B1 (en) * 1995-07-13 2005-12-27 Semiconductor Energy Laboratory Co., Ltd. Fabrication method for thin-film semiconductor
US5795829A (en) * 1996-06-03 1998-08-18 Advanced Micro Devices, Inc. Method of high density plasma metal etching
US5766971A (en) * 1996-12-13 1998-06-16 International Business Machines Corporation Oxide strip that improves planarity
US6399506B2 (en) * 1999-04-07 2002-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method for planarizing an oxide layer
US20030015496A1 (en) * 1999-07-22 2003-01-23 Sujit Sharan Plasma etching process
TWI226059B (en) * 2001-06-11 2005-01-01 Sony Corp Method for manufacturing master disk for optical recording medium having pits and projections, stamper, and optical recording medium
US6555166B2 (en) * 2001-06-29 2003-04-29 International Business Machines Method for reducing the microloading effect in a chemical vapor deposition reactor
JP4628605B2 (ja) * 2001-07-27 2011-02-09 株式会社日立製作所 デュアルダマシン用のエッチング処理方法
US6503848B1 (en) * 2001-11-20 2003-01-07 Taiwan Semiconductor Manufacturing Company Method of forming a smooth polysilicon surface using a soft etch to enlarge the photo lithography window
US20070123051A1 (en) * 2004-02-26 2007-05-31 Reza Arghavani Oxide etch with nh4-nf3 chemistry
JP5061506B2 (ja) * 2006-06-05 2012-10-31 富士電機株式会社 炭化珪素半導体装置の製造方法
JP5135885B2 (ja) * 2007-05-24 2013-02-06 富士電機株式会社 炭化珪素半導体装置の製造方法
CN102041508B (zh) * 2009-10-23 2012-07-25 中芯国际集成电路制造(上海)有限公司 刻蚀沟槽的方法
US8946812B2 (en) * 2011-07-21 2015-02-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
CN102779780B (zh) * 2012-07-25 2014-10-29 上海华力微电子有限公司 一种形成无负载效应大尺寸沟槽的方法
DE102015106441B4 (de) * 2015-04-27 2022-01-27 Infineon Technologies Ag Verfahren zum Planarisieren eines Halbleiterwafers

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JPS62293619A (ja) * 1986-06-12 1987-12-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS6350021A (ja) * 1986-08-19 1988-03-02 Nec Corp エツチング方法およびその装置
JPS6432627A (en) * 1987-07-29 1989-02-02 Hitachi Ltd Low-temperature dry etching method
JPH01292841A (ja) * 1988-05-20 1989-11-27 Hitachi Ltd 半導体装置およびその製造方法
JP2918892B2 (ja) * 1988-10-14 1999-07-12 株式会社日立製作所 プラズマエッチング処理方法
US4992137A (en) * 1990-07-18 1991-02-12 Micron Technology, Inc. Dry etching method and method for prevention of low temperature post etch deposit

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JPH04250623A (ja) 1992-09-07
JP3018517B2 (ja) 2000-03-13
US5320708A (en) 1994-06-14

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