KR970008396A - 다중합체(polymer) 제거방법 - Google Patents

다중합체(polymer) 제거방법 Download PDF

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Publication number
KR970008396A
KR970008396A KR1019950020639A KR19950020639A KR970008396A KR 970008396 A KR970008396 A KR 970008396A KR 1019950020639 A KR1019950020639 A KR 1019950020639A KR 19950020639 A KR19950020639 A KR 19950020639A KR 970008396 A KR970008396 A KR 970008396A
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KR
South Korea
Prior art keywords
treatment process
remove
polypolymer
semiconductor device
oxide layer
Prior art date
Application number
KR1019950020639A
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English (en)
Other versions
KR0168208B1 (ko
Inventor
이철규
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950020639A priority Critical patent/KR0168208B1/ko
Publication of KR970008396A publication Critical patent/KR970008396A/ko
Application granted granted Critical
Publication of KR0168208B1 publication Critical patent/KR0168208B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

반도체장치의 제조방법이 개시되어 있다. 본 발명은 반도체장치의 산화층을 건식 식각할 때 생성되는 다중합체를 제거하기 위하여 상기 산화층을 건식 식각한 직후에 산소 플라즈마 처리공정 또는 산소 래디클(radical)처리공정을 사용하여 상기 다중합체를 제거하는 것을 특징으로 한다.

Description

다중합체(polymer) 제거방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (3)

  1. 반도체장치의 제조방법에 있어서, 산화층을 건식 식각하는 단계 후에 산소 플라즈마 처리공정 또는 산소 래디클(radical) 처리공정을 실시하여, 상기 건식 식각된 표면에 생성된 다중합체를 제거하는 것을 특징으로 하는 다중합체 제거방법.
  2. 제1항에 있어서, 상기 산소 플라즈마 처리공정은 100℃ 내지 500℃의 스테이지 온도 및 5Torr 이하의 압력 분위기에서 실시하는 것을 특징으로 하는 다중합체 제거방법.
  3. 제1항에 있어서, 상기 산소 래디클 처리공정은 대기압 이하의 압력, 200LPM 이하의 오존유량, 및 100℃ 내지 500℃의 스테이지 온도 분위기에서 실시하는 것을 특징으로 하는 다중합체 제거방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950020639A 1995-07-13 1995-07-13 다중합체 제거방법 KR0168208B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950020639A KR0168208B1 (ko) 1995-07-13 1995-07-13 다중합체 제거방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950020639A KR0168208B1 (ko) 1995-07-13 1995-07-13 다중합체 제거방법

Publications (2)

Publication Number Publication Date
KR970008396A true KR970008396A (ko) 1997-02-24
KR0168208B1 KR0168208B1 (ko) 1999-02-01

Family

ID=19420551

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950020639A KR0168208B1 (ko) 1995-07-13 1995-07-13 다중합체 제거방법

Country Status (1)

Country Link
KR (1) KR0168208B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100431433B1 (ko) * 1997-06-19 2004-07-30 삼성전자주식회사 반도체 장치의 콘택홀 형성 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100431433B1 (ko) * 1997-06-19 2004-07-30 삼성전자주식회사 반도체 장치의 콘택홀 형성 방법

Also Published As

Publication number Publication date
KR0168208B1 (ko) 1999-02-01

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