US20030015496A1 - Plasma etching process - Google Patents

Plasma etching process Download PDF

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US20030015496A1
US20030015496A1 US09360292 US36029299A US20030015496A1 US 20030015496 A1 US20030015496 A1 US 20030015496A1 US 09360292 US09360292 US 09360292 US 36029299 A US36029299 A US 36029299A US 20030015496 A1 US20030015496 A1 US 20030015496A1
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Prior art keywords
plasma
etching
substrate
process
material
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US09360292
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Sujit Sharan
Gurtej S. Sandhu
Guy T. Blalock
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Micron Technology Inc
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Micron Technology Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046Dry cleaning only
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides

Abstract

In one implementation, a plasma etching process includes forming a carbon containing material over a semiconductor substrate. The carbon containing material is plasma etched from the substrate at a temperature of at least 400° C. using a hydrogen or oxygen containing plasma. In one implementation, a plasma etching process includes forming a masking layer over a substrate. The masking layer is patterned to form openings therein. Material beneath the masking layer is etched through the openings. After such etching, the masking layer is removed from the substrate. After such removing and before subsequently depositing any material over the substrate, the substrate is plasma etched at a temperature of at least 400° C. In one implementation, a semiconductor plasma etching process includes first etching material from a substrate and forming an undesired residue at least partially over the substrate during the first etching. After the first etching and before subsequently depositing any material over the substrate, the undesired residue is plasma etched from the substrate. In one implementation, a chemical vapor deposition process of depositing a material over a semiconductor substrate includes positioning a semiconductor substrate within a plasma enhanced chemical vapor deposition reactor. The substrate is plasma etched within the reactor using a first gas chemistry. After the plasma etching, a material is chemical vapor deposited over the semiconductor substrate within the reactor using a second gas chemistry without removing the substrate from the reactor between the etching and the depositing.

Description

    TECHNICAL FIELD
  • [0001]
    This invention relates to plasma etching processes and to chemical vapor deposition processes of depositing materials over semiconductor substrates.
  • BACKGROUND OF THE INVENTION
  • [0002]
    In the processing of integrated circuits, electrical contact is typically made to isolated active device regions formed within a wafer substrate typically comprising monocrystalline silicon. The active regions are typically connected by high electrically conductive paths or lines which are fabricated above an insulative material formed over the substrate surface. Further, electrical contact is also typically made to other conductive regions received outwardly of the wafer, such as to conductive lines, contact plugs and other devices. To provide electrical connection between two conductive regions, an opening in an insulative layer is typically etched to the desired regions to enable subsequently formed conductive films to make electrical connection with such regions.
  • [0003]
    The drive for integrated circuits of greater complexity, performance and reduced size has driven designers to shrink the size of devices in the horizontal plane. Yet to avoid excessive current density, the horizontal scaling has not necessarily been accompanied by a reduction in the vertical dimension. This has resulted in an increase of the ratio of device height to device width, something generally referred to as aspect ratio, and particularly with respect to contact openings.
  • [0004]
    Increased aspect ratio can result in difficulties in the overall etching process typically used to etch openings through insulative materials for making an electrical contact. For example, one common insulating material within or through which electrical contact openings are etched is borophosphosilicate glass (BPSG). A typical process for etching a contact opening in such material includes dry anisotropic etching, with or without plasma. The ever increasing aspect ratios of contact openings has been accompanied by undesired deposits or residue remaining behind on the sidewalls or base of the contact openings at the conclusion of the etch. This residue is typically in the form of a tenacious and insulative carbon polymer derived from one or both of photoresist which is undesirably removed during the etch or the etching gases themselves used to etch the contact opening through the insulator. The insulative residue at best reduces the contact area available for the desired region to which electrical connection is to be made. At worst, it can completely occlude subsequently deposited conductive material from making suitable electrical contact with the desired region. Residue material might also be present in the form of native silicon dioxide and sub-stoichiometric oxide. Such can by themselves increase contact resistance, particularly with sub-stoichiometric oxide which adversely affects silicidation when forming silicide contacts.
  • [0005]
    While the invention was principally motivated and resulted from achieving solutions to the above-identified problems, the invention is not so limited, with the scope being defined by the accompanying claims as literally worded and interpreted in accordance with the Doctrine of Equivalents.
  • SUMMARY OF THE INVENTION
  • [0006]
    The invention comprises plasma etching processes and chemical vapor deposition processes of depositing a material over a semiconductor substrate. In one implementation, a plasma etching process comprises forming a carbon containing material over a semiconductor substrate. The carbon containing material is plasma etched from the substrate at a temperature of at least 400° C. using a hydrogen or oxygen containing plasma.
  • [0007]
    In one implementation, a plasma etching process includes forming a masking layer over a substrate. The masking layer is patterned to form openings therein. Material beneath the masking layer is etched through the openings. After such etching, the masking layer is removed from the substrate. After such removing and before subsequently depositing any material over the substrate, the substrate is plasma etched at a temperature of at least 400° C.
  • [0008]
    In one implementation, a semiconductor plasma etching process comprises first etching material from a substrate and forming an undesired residue at least partially over the substrate during the first etching. After the first etching and before subsequently depositing any material over the substrate, the undesired residue is plasma etched from the substrate.
  • [0009]
    In one implementation, a chemical vapor deposition process of depositing a material over a semiconductor substrate comprises positioning a semiconductor substrate within a plasma enhanced chemical vapor deposition reactor. The substrate is plasma etched within the reactor using a first gas chemistry. After the plasma etching, a material is chemical vapor deposited over the semiconductor substrate within the reactor using a second gas chemistry without removing the substrate from the reactor between the etching and the depositing.
  • [0010]
    In one implementation, a method of forming a conductive contact includes forming an insulative material over a silicon comprising substrate. An opening is formed into the insulative material over a node location on the silicon comprising substrate to which electrical connection is desired. First plasma etching is conducted within the opening using a gas chemistry comprising hydrogen and exposing silicon of the substrate to said plasma hydrogen. After the first plasma etching, second plasma etching is conducted within the opening using a gas chemistry comprising chlorine. After the second plasma etching, a silicide material is formed within the opening in contact with silicon of the substrate.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0011]
    Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
  • [0012]
    [0012]FIG. 1 is a diagrammatic fragmentary view of a semiconductor wafer fragment at one processing step in accordance with the invention.
  • [0013]
    [0013]FIG. 2 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 1.
  • [0014]
    [0014]FIG. 3 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 2.
  • [0015]
    [0015]FIG. 4 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 3.
  • [0016]
    [0016]FIG. 5 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 4.
  • [0017]
    [0017]FIG. 6 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 5.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0018]
    This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
  • [0019]
    Referring to FIG. 1, a semiconductor wafer fragment is indicated generally with reference numeral 10. Such comprises a bulk monocrystalline silicon semiconductor substrate 12 having an exemplary conductive diffusion region 14 formed therein. In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
  • [0020]
    An electrically insulative layer 16, such as BPSG, is formed over substrate 12. A masking layer 18 is formed thereover. An example and preferred material for layer 18 is photoresist, whereby photolithography will be utilized to pattern a contact opening to diffusion region 14. Any other masking layer, whether conductive or insulative, is contemplated, with silicon dioxide and silicon nitride being examples utilized alone or in combination with other overlying masking layers. Further, no masking layer might be utilized.
  • [0021]
    Referring to FIG. 2, masking layer 18 is patterned to form openings therein (preferably therethrough), such as illustrated opening 20 over diffusion region 14.
  • [0022]
    Referring to FIG. 3, layer 16 beneath masking layer 18 through opening 20 is etched from the substrate. Such etching is preferably a dry anisotropic etch, with or without plasma, and is conducted to form an opening 21 and outwardly expose region 14, and is conducted substantially selective relative to layer 16 and region 14. An example dry etching gas chemistry would include carbon and halogen components, with CF4 being but one example. Wet or other etching could also be conducted, but the invention is described principally with respect to the above Background section-described problem which motivated the invention. Etching in the described or other manners can undesirably produce residue or deposits 22 at least partially over the substrate during the first etching, such as within the base of the contact opening as shown. Such are typically in the form of carbon containing polymers resulting from one or both of photoresist material undesirably removed during the etch or from the etching gases themselves.
  • [0023]
    The above-described and depicted processing is but one example whereby some material is etched from a substrate and an undesired residue is formed at least partially over the substrate during the etch. Such also is but one method of forming a carbon containing material over a semiconductor substrate. Alternate etchings which form a residue and alternate methods of forming carbon containing materials are of course contemplated. By way of example only, a carbon containing material might be formed over a semiconductor substrate by a deposition, cleaning, other etching or other processes. Further by way of example only, an undesired residue which may or may not be a carbon containing polymer could be formed over the substrate by other etching processes, including but not limited to wet or dry etching and etching process where conductive materials are being etched to form conductive lines or other device components.
  • [0024]
    Referring to FIG. 4, masking layer 18 has been removed from the substrate after the etching to produce opening 21.
  • [0025]
    Referring to FIG. 5 and preferably before subsequently depositing any material over the substrate, plasma etching of the substrate is conducted. Preferably, such plasma etching is conducted to remove the undesired residue from the substrate, and more preferably is conducted to be selective relative to removal of layer 16 and all other exposed material of the wafer. The plasma etching is preferably conducted at a temperature of least 400° C., and even more preferably at a temperature of at least 600° C. Further, the temperature is preferably not allowed to rise above 800° C. Pressure is preferably maintained at from 1 mTorr to 10 Torr. The plasma preferably contains hydrogen or oxygen which in the case of a carbon containing material, such as a residue comprising a carbon polymer, is effective and substantially selective in removing such material from the substrate relative to the typical oxide and silicon materials on the wafer. Hydrogen or oxygen containing plasmas could be utilized alone, or the plasma might comprise some suitable combination. Preferably, the hydrogen containing plasma is derived at least in part from one or both of H2 and NH3. Further, the plasma can predominately comprise hydrogen. Example oxygen containing plasmas can be derived from, for example, O2 and O3. The plasma might also contain other reactive or inert gases, with Ar being but one example.
  • [0026]
    A specific example process utilized a 6-liter Applied Materials Centura 5200™ single-wafer reactor, which is a parallel plate capacitively coupled reactor. Preferred power in accordance with an aspect of the invention using such a reactor is from 100 to 1000 watts, with 300 watts being utilized in this example. Wafer temperature was maintained at 635° C., with reactor pressure being held at 1.5 Torr. The gas flow to the reactor was H2 and Ar at respective flow rates of 2000 sccm and 1000 sccm. The etch was conducted on a wafer comprising a carbon polymer containing residue derived from a previous dry anisotropic etch of BPSG relative to a monocrystalline silicon substrate, with in this example a contact opening having an aspect ratio of 8:1 having previously been etched. The subsequent plasma etching was conducted for 30 seconds, and selectively removed the carbon containing polymer from the substrate relative to the otherwise exposed oxide and silicon materials.
  • [0027]
    One preferred implementation of the invention comprises conducting such plasma etching within a plasma enhanced chemical vapor deposition reactor just prior to chemical vapor depositing of a film over the wafer in such reactor with or without plasma. In a preferred implementation, a semiconductor substrate is positioned within the plasma enhanced chemical vapor deposition reactor. The substrate has some residue such as a carbon containing polymer formed at least partially thereover, and typically as the result of previous processing, for example in other equipment (i.e., the substrate of FIG. 4). Plasma etching of the substrate is conducted within the reactor using a first gas chemistry, for example, the chemistries and conditions described above (i.e., to produce the result of FIG. 5.) After the plasma etching, a material is deposited, for example chemical vapor deposited with or without plasma, over the semiconductor substrate within the reactor using a suitable second deposition gas chemistry without removing the substrate from the reactor between the etching and the depositing (i.e, to produce a layer 24 such as shown in FIG. 6). Where the plasma etching and chemical vapor depositing are conducted both subatmospheric, the substrate is preferably not exposed to atmospheric or higher pressure conditions intermediate the plasma etching and the depositing. Example preferred materials for filling contact opening 21 include silicides at the base of the contact and overlying polysilicon or tungsten. The silicide can be formed, by way of example only, by refractory metal deposition and anneal, or by chemical vapor deposition directly of the silicide.
  • [0028]
    When etching with hydrogen after contact formation over a silicon containing substrate in accordance with an aspect of the invention, it has been discovered that silicide contacts at the base of the opening can have less than optimum conductivity. Apparently, a tenacious hydrogen-silicon bond can form on the silicon from the plasma treatment. Such can lead to formation of overly thin silicide in these portions, thus leading to increased resistance. Accordingly, a preferred additional plasma etching is conducted using another gas chemistry (preferably comprising chlorine, or hydrogen and chlorine) intermediate the etching with the first gas chemistry and depositing with the second gas chemistry. The chlorine is preferably derived from one or both of Cl2 and HCl. Hydrogen might also be present from H2.
  • [0029]
    Using the above described 6-liter reactor as an example, preferred power is from 100 to 1000 watts, with 200 watts being a specific example. Wafer temperature is preferably maintained between 200° C. and 800° C., with 200° C. and 400° C. being specific examples. Pressure is preferably maintained between 1 mTorr and 100 Torr, with 5 Torr being a specific example. An example gas flow would be 100 sccm of Cl2 and 100 sccm of Ar. Where hydrogen is also being fed to the reactor, preferably at least 10% of the reactive gas flow will comprise hydrogen. One specific example would be a 1:1 volumetric flow ratio of H2 to Cl2. Etching time is preferably between 5 seconds and 30 seconds. Reduction to practice examples showed increased thickness of the silicide which was formed subsequently, increased conductivity, and lower chlorine and oxygen incorporation in the films after treatment with a chlorine containing plasma.
  • [0030]
    In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (60)

  1. 1. A plasma etching process comprising:
    forming a carbon containing material over a semiconductor substrate; and
    plasma etching the carbon containing material from the substrate at a temperature of at least 400° C. using a hydrogen or oxygen containing plasma.
  2. 2. The plasma etching process of claim 1 wherein the temperature is at least 600° C.
  3. 3. The plasma etching process of claim 1 wherein the plasma contains hydrogen and oxygen.
  4. 4. The plasma etching process of claim 1 wherein the plasma contains oxygen.
  5. 5. The plasma etching process of claim 1 wherein the plasma contains hydrogen.
  6. 6. The plasma etching process of claim 5 wherein the hydrogen containing plasma is derived at least in part from H2.
  7. 7. The plasma etching process of claim 5 wherein the hydrogen containing plasma is derived at least in part from NH3.
  8. 8. The plasma etching process of claim 5 wherein the carbon containing material comprises a polymer.
  9. 9. The plasma etching process of claim 1 wherein the plasma is predominately comprised of hydrogen.
  10. 10. The plasma etching process of claim 1 further comprising after said plasma etching, further plasma etching using a gas comprising chlorine.
  11. 11. The plasma etching process of claim 10 further comprising after said plasma etching, further plasma etching using a gas comprising a mixture of chlorine and hydrogen.
  12. 12. The plasma etching process of claim 10 further comprising after said plasma etching, further plasma etching using a gas comprising a mixture of Cl2 and H2.
  13. 13. The plasma etching process of claim 10 wherein the chlorine is derived at least in part from Cl2.
  14. 14. The plasma etching process of claim 10 wherein the chlorine is derived at least in part from HCl.
  15. 15. A plasma etching process comprising:
    forming a masking layer over a substrate;
    patterning the masking layer to form openings therein;
    first etching material beneath the masking layer through the openings;
    after the first etching, removing the masking layer from the substrate; and
    after the removing and before subsequently depositing any material over the substrate, plasma etching the substrate at a temperature of at least 400° C.
  16. 16. The plasma etching process of claim 15 wherein the plasma comprises oxygen.
  17. 17. The plasma etching process of claim 15 wherein the plasma comprises hydrogen.
  18. 18. The plasma etching process of claim 17 wherein the hydrogen containing plasma is derived at least in part from H2.
  19. 19. The plasma etching process of claim 17 wherein the hydrogen containing plasma is derived at least in part from NH3.
  20. 20. The plasma etching process of claim 15 wherein the plasma is predominately comprised of hydrogen.
  21. 21. The plasma etching process of claim 15 wherein the temperature is at least 600° C.
  22. 22. The plasma etching process of claim 15 wherein the first etching leaves a residue at least partially over the substrate, the plasma etching removing the residue from the substrate.
  23. 23. The plasma etching process of claim 15 comprising after the removing and before subsequently depositing any material over the substrate, conducting at least two plasma etchings using different reactive gas chemistries, one of the at least two plasma etchings being said plasma etching at a temperature of at least 400° C., another of the at least two plasma etchings being subsequent to the one and using a gas chemistry comprising chlorine.
  24. 24. The plasma etching process of claim 23 wherein the another plasma etching is conducted at a temperature of at least 400° C.
  25. 25. A semiconductor plasma etching process comprising:
    first etching material from a substrate and forming an undesired residue at least partially over the substrate during the first etching; and
    after the first etching and before subsequently depositing any material over the substrate, plasma etching the undesired residue from the substrate.
  26. 26. The plasma etching process of claim 25 wherein the first etching comprises dry etching.
  27. 27. The plasma etching process of claim 25 wherein the first etching comprises wet etching.
  28. 28. The plasma etching process of claim 25 wherein the residue comprises a carbon containing polymer.
  29. 29. The plasma etching process of claim 25 wherein the residue is not a polymer.
  30. 30. The plasma etching process of claim 25 wherein the plasma etching is conducted at a temperature of at least 400° C.
  31. 31. The plasma etching process of claim 25 wherein the plasma etching is conducted at a temperature of at least 600° C.
  32. 32. The plasma etching process of claim 25 wherein the plasma etching is conducted substantially selective to remove the residue relative to all other exposed material of the substrate.
  33. 33. The plasma etching process of claim 25 wherein the residue comprises a carbon containing polymer, and the plasma etching is conducted at a temperature of at least 400° C.
  34. 34. The plasma etching process of claim 25 wherein the residue comprises a carbon containing polymer, and the plasma etching is conducted at a temperature of at least 600° C.
  35. 35. A plasma etching process comprising:
    forming a photoresist layer over a semiconductor substrate;
    patterning the photoresist layer to form openings therethrough;
    dry etching a first layer immediately beneath the photoresist layer through the openings and forming a carbon containing polymer residue at least partially over the substrate during the first etching;
    after the dry etching, removing the photoresist layer from the substrate; and
    after the removing and before subsequently depositing any material over the substrate, plasma etching the carbon containing polymer residue from the substrate substantially selectively relative to the first layer.
  36. 36. The plasma etching process of claim 35 wherein the plasma etching is conducted at a temperature of at least 400° C.
  37. 37. The plasma etching process of claim 35 wherein the plasma etching is conducted at a temperature of at least 600° C.
  38. 38. The plasma etching process of claim 35 wherein the plasma comprises oxygen.
  39. 39. The plasma etching process of claim 35 wherein the plasma comprises hydrogen.
  40. 40. The plasma etching process of claim 39 wherein the plasma is derived at least in part from H2.
  41. 41. The plasma etching process of claim 39 wherein the plasma is derived at least in part from NH3.
  42. 42. A chemical vapor deposition process of depositing a material over a semiconductor substrate comprising:
    positioning a semiconductor substrate within a plasma enhanced chemical vapor deposition reactor;
    plasma etching the substrate within the reactor using a first gas chemistry; and
    after the plasma etching, chemical vapor depositing a material over the semiconductor substrate within the reactor using a second gas chemistry without removing the substrate from the reactor between the etching and the depositing.
  43. 43. The plasma etching process of claim 42 wherein the plasma etching and the depositing are conducted at subatmospheric pressure, the substrate not being exposed to atmospheric pressure intermediate the plasma etching and the depositing.
  44. 44. The plasma etching process of claim 42 wherein the plasma etching is conducted at a temperature of at least 400° C.
  45. 45. The plasma etching process of claim 42 wherein the plasma etching is conducted at a temperature of at least 600° C.
  46. 46. The plasma etching process of claim 42 wherein the first chemistry comprises oxygen.
  47. 47. The plasma etching process of claim 42 wherein the first chemistry comprises hydrogen.
  48. 48. The plasma etching process of claim 42 wherein the substrate has a residue formed at least partially thereover the result of previous processing, the plasma etching removing the residue from the substrate.
  49. 49. The plasma etching process of claim 42 wherein the substrate has a carbon containing polymer formed at least partially thereover, the plasma etching removing the carbon containing polymer from the substrate.
  50. 50. The plasma etching process of claim 42 wherein the substrate has a carbon containing polymer residue formed at least partially thereover the result of previous processing, the plasma etching removing the carbon containing polymer residue from the substrate.
  51. 51. The plasma etching process of claim 42 comprising plasma etching the substrate within the reactor using another gas chemistry different from the first and second gas chemistries intermediate the plasma etching with the first gas chemistry and the depositing.
  52. 52. The plasma etching process of claim 51 wherein the another gas chemistry comprises chlorine.
  53. 53. The plasma etching process of claim 52 wherein the another gas chemistry comprises hydrogen.
  54. 54. A method of forming a conductive contact comprising:
    forming an insulative material over a silicon comprising substrate;
    forming an opening into the insulative material over a node location on the silicon comprising substrate to which electrical connection is desired;
    first plasma etching within the opening using a gas chemistry comprising hydrogen and exposing silicon of the substrate to said plasma hydrogen;
    after the first plasma etching, second plasma etching within the opening using a gas chemistry comprising chlorine; and
    after the second plasma etching, forming a silicide material within the opening in contact with silicon of the substrate.
  55. 55. The method of claim 54 wherein the silicide material is formed by refractory metal deposition and anneal.
  56. 56. The method of claim 54 wherein the silicide material is formed by chemical vapor deposition of the silicide material.
  57. 57. The method of claim 54 wherein the gas chemistry comprising hydrogen comprises H2.
  58. 58. The method of claim 54 wherein the gas chemistry comprising chlorine comprises Cl2.
  59. 59. The method of claim 54 wherein the gas chemistry comprising chlorine comprises HCl.
  60. 60. The method of claim 54 wherein the first plasma etching, the second plasma etching, and at least some of the silicide material forming all occur in the same chamber.
US09360292 1999-07-22 1999-07-22 Plasma etching process Abandoned US20030015496A1 (en)

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US7022618B2 (en) 2006-04-04 grant
US20040063314A1 (en) 2004-04-01 application
US20020040886A1 (en) 2002-04-11 application

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