KR20050041423A - Method for forming salicide layer - Google Patents
Method for forming salicide layer Download PDFInfo
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- KR20050041423A KR20050041423A KR1020030076590A KR20030076590A KR20050041423A KR 20050041423 A KR20050041423 A KR 20050041423A KR 1020030076590 A KR1020030076590 A KR 1020030076590A KR 20030076590 A KR20030076590 A KR 20030076590A KR 20050041423 A KR20050041423 A KR 20050041423A
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
본 발명은 살리사이드막 형성방법에 관한 개시한 것으로서, PMOS영역과 NMOS영역이 정의된 반도체기판을 제공하는 단계와, 기판 전면에 불순물이 도핑된 다결정 실리콘막을 형성하는 단계와, 실리콘막을 선택 식각하여 상기 PMOS영역과 NMOS영역에 각각 PMOS용 게이트와 NMOS용 게이트를 형성하는 단계와, PMOS용 게이트와 NMOS용 게이트의 양측면에 각각 절연 스페이서를 형성하는 단계와, PMOS영역을 덮고 NMOS영역을 노출시킨 다음, 상기 기판 전면에 N+ 이온주입을 실시하여 NMOS용 게이트 하부의 양측 기판에 N형 소오스/드레인을 형성하는 단계와, NMOS영역을 덮고 PMOS영역을 노출시킨 다음, 상기 기판 전면에 P+이온주입을 실시하여 제 PMOS용 게이트 하부의 양측 기판에 P형 소오스/드레인을 형성하는 단계와, 상기 구조의 기판 전면에 실리사이드 형성용 물질층을 형성하는 단계와, 실리사이드 형성용 물질층을 살리사이드 공정을 진행하여 N형,P형 소오스/드레인, 상기 NMOS용 게이트 및 PMOS용 게이트 표면에 선택적으로 살리사이드막을 형성하는 단계와, 미반응된 실리사이드 형성용 물질층을 습식 식각하는 단계와, 결과물에 플라즈마 건식 세정 공정을 실시하여 상기 PMOS용 게이트, NMOS용 게이트 및 N형,P형 소오스/드레인의 표면을 평탄화하는 단계를 포함한다.The present invention relates to a method for forming a salicide film, comprising the steps of: providing a semiconductor substrate having a PMOS region and an NMOS region defined therein; forming a polycrystalline silicon film doped with impurities on the entire surface of the substrate; Forming a PMOS gate and an NMOS gate in the PMOS region and the NMOS region, forming insulating spacers on both sides of the PMOS gate and the NMOS gate, respectively, exposing the PMOS region and exposing the NMOS region. Performing N + ion implantation on the entire surface of the substrate to form N-type sources / drains on both substrates under the NMOS gate; exposing the PMOS region by covering the NMOS region; and then performing P + ion implantation on the entire surface of the substrate. Forming a P-type source / drain on both substrates below the PMOS gate, and forming a silicide-forming material layer on the entire substrate of the structure. Forming a salicide layer on the surface of the N-type and P-type source / drain, the NMOS gate and the PMOS gate by performing a salicide process on the silicide-forming material layer, and unreacted silicide Wet etching the forming material layer, and performing a plasma dry cleaning process on the resultant to planarize the surfaces of the PMOS gate, the NMOS gate, and the N-type and P-type source / drain.
Description
본 발명은 반도체소자의 형성방법에 관한 것으로, 보다 구체적으로는 반도체소자의 살리사이드(SALICIDE:Self ALIgned SiliCIDE) 공정을 진행하는 데 있어서, 살리사이드막 표면이 불균일해지는 것을 방지하여 전기적 특성을 향상시킬 수 있는 살리사이드막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and more particularly, in the process of salicide (SALICIDE: Self-Aligned SiliCIDE) of a semiconductor device, the surface of the salicide layer is prevented from being uneven to improve electrical characteristics. It relates to a method for forming a salicide film.
일반적으로, 고속의 반도체 소자를 구성하기 위하여 게이트 전극과 소오스/드레인 영역의 면저항과 콘택 저항을 감소시켜야 한다.In general, the sheet resistance and the contact resistance of the gate electrode and the source / drain regions should be reduced to form a high speed semiconductor device.
이를 위하여, 게이트 전극과 소오스/드레인 영역에만 선택적으로 비저항이 낮은 실리사이드(silicide)를 형성시키는 살리사이드 공정이 널리 사용되고 있다.For this purpose, a salicide process for forming silicide with low resistivity selectively in the gate electrode and the source / drain regions is widely used.
특히 1G 이상의 DRAM 또는 로직(logic) 및 통합 메모리 로직(Merged Memory Logic; MML) 소자 등의 게이트 특성을 향상시키기 위해 살리사이드 게이트 공정이 많이 적용되고 있다.In particular, salicide gate processes have been widely applied to improve gate characteristics of 1G DRAM or more logic and integrated memory logic (MML) devices.
도 1a 내지 도 1e는 종래기술에 따른 살리사이드막 형성방법을 설명하기 위한 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a salicide layer according to the related art.
종래기술에 따른 살리사이드막 형성방법은, 도 1a에 도시된 바와 같이, PMOS영역과 NMOS영역이 정의된 반도체기판(1) 상에 실리콘 산화막(3)을 15∼30Å두께로 증착한다. 여기서, 상기 반도체기판(1)에 STI(Shallow Trench Isolation) 및 웰(well) 형성 공정은 생략하기로 한다.In the method for forming a salicide film according to the prior art, as shown in FIG. 1A, a silicon oxide film 3 is deposited to a thickness of 15 to 30 microseconds on a semiconductor substrate 1 on which a PMOS region and an NMOS region are defined. Here, the process of forming shallow trench isolation (STI) and wells in the semiconductor substrate 1 will be omitted.
이어, 상기 실리콘 산화막(3) 위에 불순물이 도핑된 다결정 실리콘막(5)을 1500∼2500Å두께로 증착한다. 그런 다음, 상기 다결정 실리콘막(5) 위에 감광막(미도시)을 도포하고 노광 및 현상하여 게이트 형성영역을 노출시키는 감광막 패턴(9)을 형성한다. Subsequently, a polycrystalline silicon film 5 doped with impurities is deposited on the silicon oxide film 3 to a thickness of 1500 to 2500 Å. Then, a photoresist film (not shown) is applied on the polycrystalline silicon film 5 to expose and develop a photoresist pattern 9 that exposes the gate formation region.
이 후, 도 1b에 도시된 바와 같이, 상기 감광막 패턴을 마스크로 하여 상기 불순물이 도핑된 다결정 실리콘막을 식각하여 NMOS영역과 PMOS영역에 각각 NMOS용 게이트(6a) 및 PMOS용 게이트(6b)를 형성한 다음, 상기 감광막 패턴을 제거한다.Subsequently, as shown in FIG. 1B, the impurity-doped polycrystalline silicon film is etched using the photoresist pattern as a mask to form an NMOS gate 6a and a PMOS gate 6b in an NMOS region and a PMOS region, respectively. Then, the photoresist pattern is removed.
이어, 도 1c에 도시된 바와 같이, 상기 게이트 구조 전면에 실리콘 질화막(미도시)을 증착하고 나서, 상기 기판 표면이 노출되는 시점까지 실리콘 질화막 및 실리콘 산화막을 에치백(etch back)하여 각각의 NMOS용 게이트(6a) 및 PMOS용 게이트(6b)의 양측면에 절연 스페이서(7)를 형성한다. 이때, 도면부호 4는 게이트절연막을 나타낸 것이다.Subsequently, as illustrated in FIG. 1C, a silicon nitride film (not shown) is deposited on the entire surface of the gate structure, and the silicon nitride film and the silicon oxide film are etched back until the surface of the substrate is exposed. Insulating spacers 7 are formed on both sides of the gate 6a and the PMOS gate 6b. At this time, reference numeral 4 denotes a gate insulating film.
그런 다음, 감광막을 이용하여 PMOS영역을 덮고 NMOS영역을 노출시킨 다음, 기판 전면에 N+ 이온주입을 실시하여 NMOS용 게이트(6a) 하부의 양측 기판에 N형 소오스/드레인(a)을 형성한다. 그런 다음, 이와는 반대로, NMOS영역을 덮고 PMOS영역을 노출시킨 다음, 기판 전면에 P+이온주입을 실시하여 제 PMOS용 게이트(6b) 하부의 양측 기판에 P형소오스/드레인(b)을 형성한다.Then, the PMOS region is covered using the photoresist film and the NMOS region is exposed. Then, N + ion implantation is performed on the entire surface of the substrate to form N-type source / drain a on both substrates under the NMOS gate 6a. Then, on the contrary, the PMOS region is covered and the PMOS region is exposed, and then P + ion implantation is performed on the entire surface of the substrate to form P-type sources / drains b on both substrates under the PMOS gate 6b.
이 후, 도 1d에 도시된 바와 같이, 상기 구조의 기판 전면에 Ge이온을 이온주입을 실시한다. 이때, 상기 Ge이온 주입 공정은 NMOS용 게이트(6a), PMOS용 게이트(6b)의 다결정 실리콘 그레인 크기를 변경시켜 살리사이드의 균일도를 향상시키기 위한 것으로서, 시트저항을 개선시키는 역할을 한다. Thereafter, as illustrated in FIG. 1D, ion implantation of Ge ions is performed on the entire surface of the substrate having the structure. In this case, the Ge ion implantation process is to improve the uniformity of the salicide by changing the size of the polycrystalline silicon grains of the NMOS gate 6a and the PMOS gate 6b, and serves to improve sheet resistance.
이어, 도 1e에 도시된 바와 같이, 상기 결과물 전면에 고융점 금속, 예를들면, Co, Ti등의 물질을 증착하여 실리사이드 형성용 물질층(미도시)을 형성하고 나서, 상기 실리사이드 형성용 물질층(미도시)에 열처리를 포함한 살리사이드 공정을 진행하여 NMOS용 게이트(6a), PMOS용 게이트(6b), N형 소오스/드레인(a) 및 P형 소오스/드레인(b) 표면에 살리사이드막(8)을 형성한다. 이때, 미반응된 실리사이드 형성용 물질층을 습식 식각하여 제거한다.Subsequently, as shown in FIG. 1E, a high melting point metal, for example, Co or Ti, is deposited on the entire surface of the resultant to form a silicide forming material layer (not shown), and then the silicide forming material. A salicide process including a heat treatment is performed on the layer (not shown) to form a salicide on the NMOS gate 6a, the PMOS gate 6b, the N-type source / drain (a), and the P-type source / drain (b) surface. The film 8 is formed. At this time, the unreacted silicide-forming material layer is removed by wet etching.
도 2는 종래 기술에 따른 문제점을 설명하기 위한 공정단면도이다. Figure 2 is a process cross-sectional view for explaining the problem according to the prior art.
상술한 바와 같이, 종래의 기술에서는 살리사이드 공정을 진행하기 이전에 Ge이온 주입 공정을 진행시켜 살리사이드막이 형성될 부위의 입자 크기를 변경시켜 살리사이드의 균일도를 향상시키기 위한 것으로서, 시트저항을 개선시키는 방법을 적용하였다.As described above, the prior art is to improve the uniformity of the salicide by changing the particle size of the region where the salicide film is to be formed by performing a Ge ion implantation process prior to the salicide process, thereby improving sheet resistance. The method was applied.
그러나, Ge이온 주입 공정을 진행시킴에도 불구하고, 살리사이드 형성 공정 시에 열처리 등의 공정 조건에 의해 살리사이드막이 불균일하게 형성되며, 이로써, PMOS용 게이트의 그레인 사이에 자연산화막 및 오염물질이 형성되고, 이로 인해 살리사이드막이 불균일하게 형성되거나 뭉침 현상(agglomerate)이 발생될 수 있다.However, despite the Ge ion implantation process, the salicide film is non-uniformly formed by process conditions such as heat treatment during the salicide formation process, thereby forming a natural oxide film and contaminants between the grains of the PMOS gate. As a result, the salicide layer may be unevenly formed or agglomerates may occur.
특히, NMOS영역에 비해 PMOS영역에서 살리사이드막이 더 불균일하게 형성되는데, 그 이유는 PMOS용 게이트의 그레인이 NMOS용 게이트의 그레인과 비교하여 상대적으로 거칠기 때문이다. 이와 같이 불균일하게 형성된 살리사이드막은 소자 결함 또는 필드 산화막에서의 누설 전류 등의 문제를 야기시킨다.In particular, the salicide film is more nonuniform in the PMOS region than in the NMOS region because the grain of the PMOS gate is relatively rough compared with that of the NMOS gate. The non-uniformly formed salicide film causes problems such as device defects or leakage currents in the field oxide film.
따라서, 이러한 문제점을 해결하기 위해, 미반응된 실리사이드 형성용 물질층을 습식식각 시간을 길게 하게되면 PMOS영역 내의 PMOS용 게이트 및 P형 소오스/드레인에 살리사이드막이 정상적으로 생성된다. 그러나, 상기 습식식각 시간을 길게 하면 필드영역의 손상을 가져오게 되므로, 누설 전류를 야기시키며, 또한, 이 과정에서, 과도 식각하게 되면, PMOS용 게이트 및 P형 소오스/드레인이 손실되어 디바이스의 열화를 가져온다. Therefore, in order to solve this problem, when the unreacted silicide forming material layer is wet-etched for a long time, a salicide film is normally formed in the PMOS gate and the P-type source / drain in the PMOS region. However, prolonging the wet etching time causes damage to the field region, which causes leakage current, and in the process, excessive etching causes loss of PMOS gate and P-type source / drain, resulting in deterioration of the device. Bring it.
따라서, 상기 문제점을 해결하고자, 본 발명의 목적은 살리사이드 공정 이후 살리사이드막이 형성된 부위에 Ar가스를 이용한 플라즈마 방식의 건식 세정 공정을 실시함으로써, 살리사이드막의 균일도를 개선시킬 수 있는 살리사이드막 형성방법을 제공하려는 것이다.Therefore, in order to solve the above problems, an object of the present invention is to form a salicide film that can improve the uniformity of the salicide film by performing a dry cleaning process using Ar gas on a portion where the salicide film is formed after the salicide process. To provide a way.
상기 목적을 달성하고자, 본 발명의 살리사이드막 형성방법은 PMOS영역과 NMOS영역이 정의된 반도체기판을 제공하는 단계와, 기판 전면에 불순물이 도핑된 다결정 실리콘막을 형성하는 단계와, 실리콘막을 선택 식각하여 상기 PMOS영역과 NMOS영역에 각각 PMOS용 게이트와 NMOS용 게이트를 형성하는 단계와, PMOS용 게이트와 NMOS용 게이트의 양측면에 각각 절연 스페이서를 형성하는 단계와, PMOS영역을 덮고 NMOS영역을 노출시킨 다음, 상기 기판 전면에 N+ 이온주입을 실시하여 NMOS용 게이트 하부의 양측 기판에 N형 소오스/드레인을 형성하는 단계와, NMOS영역을 덮고 PMOS영역을 노출시킨 다음, 상기 기판 전면에 P+이온주입을 실시하여 제 PMOS용 게이트 하부의 양측 기판에 P형 소오스/드레인을 형성하는 단계와, 상기 구조의 기판 전면에 실리사이드 형성용 물질층을 형성하는 단계와, 실리사이드 형성용 물질층을 살리사이드 공정을 진행하여 N형,P형 소오스/드레인, 상기 NMOS용 게이트 및 PMOS용 게이트 표면에 선택적으로 살리사이드막을 형성하는 단계와, 미반응된 실리사이드 형성용 물질층을 습식 식각하는 단계와, 결과물에 플라즈마 건식 세정 공정을 실시하여 상기 PMOS용 게이트, NMOS용 게이트 및 N형,P형 소오스/드레인의 표면을 평탄화하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, the method of forming a salicide film according to the present invention includes providing a semiconductor substrate having a PMOS region and an NMOS region, forming a polycrystalline silicon film doped with impurities on the entire surface of the substrate, and selectively etching the silicon film. Forming a PMOS gate and an NMOS gate in the PMOS region and the NMOS region, forming insulating spacers on both sides of the PMOS gate and the NMOS gate, respectively, and covering the PMOS region and exposing the NMOS region. Next, N + ion implantation is performed on the entire surface of the substrate to form N-type sources / drains on both substrates below the gate for NMOS. Forming a P-type source / drain on both substrates under the PMOS gate, and forming a silicide-forming material layer on the entire substrate of the structure And forming a salicide layer on the surface of the N-type and P-type source / drain, the NMOS gate and the PMOS gate by performing a salicide process on the silicide-forming material layer. Wet etching the forming material layer, and performing a plasma dry cleaning process on the resultant to planarize the surfaces of the PMOS gate, the NMOS gate, and the N-type and P-type source / drain.
상기 미반응된 실리사이드 형성용 물질층의 습식 식각 공정과 상기 플라즈마 건식 세정 공정은 인-시튜로 진행하는 것이 바람직하다.The wet etching process of the unreacted silicide forming material layer and the plasma dry cleaning process may be performed in-situ.
상기 플라즈마 건식 세정 공정에서, 플라즈마는 아르곤 가스를 이용하는 것이 바람직하다. 또한, 상기 플라즈마 건식 세정 공정 조건은, 바람직하게는, 1000mTorr의 압력과 2000W의 전압을 가한다.In the plasma dry cleaning process, the plasma preferably uses argon gas. In addition, the plasma dry cleaning process conditions are preferably to apply a pressure of 1000mTorr and a voltage of 2000W.
(실시예)(Example)
이하, 첨부된 도면을 참고로 하여 본 발명에 따른 살리사이드막 형성방법을 설명하기로 한다.Hereinafter, a method for forming a salicide film according to the present invention will be described with reference to the accompanying drawings.
도 3a 내지 도 3e는 본 발명에 따른 살리사이드막 형성방법을 설명하기 위한 공정단면도이다.3A to 3E are cross-sectional views illustrating a method of forming a salicide film according to the present invention.
본 발명에 따른 살리사이드막 형성방법은, 도 3a에 도시된 바와 같이, NMOS영역 및 PMOS영역이 정의된 반도체기판(10)을 제공한다. 이어, 상기 기판(10) 전면에 실리콘 산화막(12) 및 불순물이 도핑된 다결정실리콘막(14)을 차례로 형성한다. The method for forming a salicide film according to the present invention provides a semiconductor substrate 10 in which an NMOS region and a PMOS region are defined, as shown in FIG. 3A. Subsequently, the silicon oxide film 12 and the polysilicon film 14 doped with impurities are sequentially formed on the entire surface of the substrate 10.
이때, 상기 실리콘 산화막(12)은 15∼30Å두께로 형성하고, 상기 불순물이 도핑된 다결정 실리콘막(14)은 1500∼2500Å두께로 형성한다. In this case, the silicon oxide film 12 is formed to have a thickness of 15 to 30 kPa, and the polycrystalline silicon film 14 doped with the impurity is formed to have a thickness of 1500 to 2500 kPa.
이어, 상기 다결정 실리콘막(14) 위에 감광막을 도포하고, 노광 및 현상하여 PMOS용 게이트영역 및 NMOS용 게이트영역을 노출시키는 감광막 패턴(19)을 형성한다.Subsequently, a photosensitive film is coated on the polycrystalline silicon film 14, and then exposed and developed to form a photosensitive film pattern 19 exposing the PMOS gate region and the NMOS gate region.
그런 다음, 도 3b에 도시된 바와 같이, 상기 감광막 패턴을 마스크로 하여 상기 다결정 실리콘막을 식각하여 각각 NMOS용 게이트(15a)와 PMOS용 게이트(15b)를 형성한다. 이후, 감광막 패턴을 제거한다.3B, the polycrystalline silicon film is etched using the photoresist pattern as a mask to form an NMOS gate 15a and a PMOS gate 15b, respectively. Thereafter, the photoresist pattern is removed.
이어, 도 3c에 도시된 바와 같이, 상기 게이트 구조 전면에 실리콘 질화막(미도시)을 증착하고 나서, 상기 실리콘 질화막 및 실리콘 산화막을 에치백하여 게이트산화막(13) 및 NMOS용 게이트(15a)와 PMOS용 게이트(15b)의 양측면에 각각 절연 스페이서(16)를 형성한다.Subsequently, as shown in FIG. 3C, a silicon nitride film (not shown) is deposited on the entire gate structure, and the silicon nitride film and the silicon oxide film are etched back to form a gate oxide film 13, an NMOS gate 15a, and a PMOS. Insulating spacers 16 are formed on both sides of the gate 15b.
그런 다음, 감광막을 이용하여 PMOS영역을 덮고 NMOS영역을 노출시킨 다음, 기판 전면에 N+ 이온주입을 실시하여 NMOS용 게이트(15a) 하부의 양측 기판에 N형 소오스/드레인(c)을 형성한다. 그런 다음, 이와는 반대로, NMOS영역을 덮고 PMOS영역을 노출시킨 다음, 기판 전면에 P+이온주입을 실시하여 제 PMOS용 게이트(15b) 하부의 양측 기판에 P형소오스/드레인(d)을 형성한다. Then, the PMOS region is covered using the photoresist film, the NMOS region is exposed, and then N + ion implantation is performed on the entire surface of the substrate to form N-type sources / drains c on both substrates under the NMOS gate 15a. Then, on the contrary, after covering the NMOS region and exposing the PMOS region, P + ion implantation is performed on the entire surface of the substrate to form P-type sources / drains d on both substrates below the PMOS gate 15b.
이때, PMOS용 게이트와 NMOS용 게이트의 다결정 실리콘 그레인 사이에는 자연산화막(미도시)이 형성되어져 있다. 특히, NMOS용 게이트에 비해 PMOS용 게이트의 다결정 실리콘 그레인이 훨씬 크다. 따라서, 상기 그레인 사이에 형성된 자연산화막 및 오염물질은 이후의 살리사이드막의 형성을 방해하여 균일하지 못하게 하는 역할을 한다.At this time, a natural oxide film (not shown) is formed between the polycrystalline silicon grains of the PMOS gate and the NMOS gate. In particular, the polycrystalline silicon grain of the PMOS gate is much larger than that of the NMOS gate. Therefore, the natural oxide film and the contaminants formed between the grains serve to prevent the formation of the salicide layer to be uniform.
이후, 도 3d에 도시된 바와 같이, 상기 결과물 전면에 고융점 금속, 예를들면, Co, Ti등의 물질을 증착하여 실리사이드 형성용 물질층(미도시)을 형성하고 나서, 상기 실리사이드 형성용 물질층(미도시)에 살리사이드 공정을 진행하여 NMOS용 게이트(15a), PMOS용 게이트(15b), N형 소오스/드레인(c) 및 P형 소오스/드레인(d) 표면에 살리사이드막(18)을 형성한다. 이어, 미반응된 실리사이드 형성용 물질층을 습식 식각하여 제거한다. Then, as shown in Figure 3d, by depositing a material such as high melting point metal, for example, Co, Ti on the entire surface of the resultant to form a silicide forming material layer (not shown), and then the silicide forming material A salicide process is performed on the layer (not shown) to form a salicide film 18 on the NMOS gate 15a, the PMOS gate 15b, the N-type source / drain (c), and the P-type source / drain (d). ). Subsequently, the unreacted silicide formation material layer is removed by wet etching.
그런 다음, 도 3d에 도시된 바와 같이, 상기 실리사이드 형성용 물질층의 습식 식각 공정 후 인-시튜(in-situ)로 상기 결과물 전면에 플라즈마를 이용한 건식 세정 공정(17)을 진행하여 살리사이드막 형성을 방해하는 인자인 자연산화막 등의 오염물질을 제거한다. 이때, 상기 건식 세정 공정(17)은 1000mTorr의 높은 압력과 2000W의 전압을 가하며, 플라마즈로는 Ar가스를 이용한다. Then, as shown in Figure 3d, after the wet etching process of the silicide-forming material layer proceeds to a dry cleaning process (17) using a plasma on the entire surface of the resultant in-situ to the salicide layer Removes contaminants such as natural oxides, which interfere with formation. In this case, the dry cleaning process 17 applies a high pressure of 1000 mTorr and a voltage of 2000 W, and uses Ar gas as a plasma.
상술한 플라즈마를 이용한 건식 세정 공정의 원리는 다음과 같다.The principle of the dry cleaning process using the above-described plasma is as follows.
불활성의 Ar가스는 무선주파수(radio frequency)의 방전으로 활성화되면서 기판 표면의 유기 및 무기오염, 자연산화막과의 순수한 물리적 반응에 의해 상기 오염된 표면의 불순물만 제거한다. 이때, Ar가스 대신 산소나 수소를 이용하면 산화나 환원반응 등 오염물 제거 이외의 원하지 않는 부차적인 화학반응이 일어나게 된다. 한편, 불활성의 Ar가스를 이용한 플라즈마 방식의 건식 세정 공정은 오염물 제거 이외에도 표면을 플라즈마 할성화시켜 주기 때문에 미세한 요철을 형성시켜 접착물질과 계면 사이에서 접착력 증대 효과를 줄 수 있다.The inert Ar gas is activated by radio frequency discharge and removes only impurities on the contaminated surface by pure physical reaction with organic and inorganic pollution and natural oxide film on the substrate surface. At this time, if oxygen or hydrogen is used instead of Ar gas, unwanted secondary chemical reactions other than removal of contaminants such as oxidation or reduction reactions occur. On the other hand, the plasma-type dry cleaning process using an inert Ar gas can make the surface plasma-activated in addition to the removal of contaminants, thereby forming fine concavities and convexities, thereby increasing the adhesion between the adhesive material and the interface.
본 발명에 따르면, 미반응된 실리사이드 형성용 물질층을 습식 식각하여 제거한 후, 인-시튜로 Ar가스를 이용한 플라즈마 방식의 건식 세정 공정을 진행함으로써, 기판 표면 및 NMOS용 게이트(15a)와 PMOS용 게이트(15b)의 다결정 실리콘 그레인 사이의 유기 및 무기오염, 자연산화막이 잔류되는 것을 억제하고, 이로써, 살리사이드막의 균일도를 향상시킨다. According to the present invention, by removing the unreacted silicide-forming material layer by wet etching and then performing a dry cleaning process using an Ar gas in-situ, the substrate surface, the gate for NMOS 15a and the PMOS for The organic and inorganic contamination between the polycrystalline silicon grains of the gate 15b and the natural oxide film are suppressed from remaining, thereby improving the uniformity of the salicide film.
이상에서와 같이, 본 발명은 살리사이드막 형성 공정 후의 미반응된 실리사이드 형성용 물질층을 습식 식각하여 제거한 다음, 인-시튜로 Ar가스를 이용한 플라즈마 방식의 건식 세정 공정을 진행함으로써, 살리사이드막이 형성된 부위의 오염물질을 제거하여 살리사이드막의 균일도를 향상시키는 한편, 상기 살리사이드막이 형성된 부위의 표면을 플라즈마 할성화시켜 미세한 요철을 형성시키기 때문에 접착물질과 계면 사이에서 접착력 증대 효과를 줄 수 있다.As described above, in the present invention, by removing the unreacted silicide forming material layer after the salicide film forming process by wet etching, the salicide film is formed by performing a dry cleaning process using an Ar gas in-situ. By removing contaminants in the formed region to improve the uniformity of the salicide layer, plasma activation of the surface of the region where the salicide layer is formed to form fine concavities and convexities can increase the adhesion between the adhesive material and the interface.
따라서, 본 발명은 게이트의 시트저항 및 열안정성에 우수한 디바이스의 전기적 특성을 향상시킬 수 있다.Therefore, the present invention can improve the electrical characteristics of the device excellent in the sheet resistance and thermal stability of the gate.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
도 1a 내지 도 1e는 종래기술에 따른 살리사이드막 형성방법을 설명하기 위한 공정단면도.1A to 1E are cross-sectional views illustrating a method of forming a salicide film according to the related art.
도 2는 종래 기술에 따른 문제점을 설명하기 위한 공정단면도.Figure 2 is a process cross-sectional view for explaining the problem according to the prior art.
도 3a 내지 도 3e는 본 발명에 따른 살리사이드막 형성방법을 설명하기 위한 공정단면도.3A to 3E are cross-sectional views illustrating a method of forming a salicide film according to the present invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030076590A KR100575620B1 (en) | 2003-10-31 | 2003-10-31 | method for forming salicide layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020030076590A KR100575620B1 (en) | 2003-10-31 | 2003-10-31 | method for forming salicide layer |
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| Publication Number | Publication Date |
|---|---|
| KR20050041423A true KR20050041423A (en) | 2005-05-04 |
| KR100575620B1 KR100575620B1 (en) | 2006-05-03 |
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| KR1020030076590A KR100575620B1 (en) | 2003-10-31 | 2003-10-31 | method for forming salicide layer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100827435B1 (en) * | 2006-01-31 | 2008-05-06 | 삼성전자주식회사 | Method of fabricating gate with oxygen free ashing process in semiconductor device |
| US8201784B2 (en) * | 2007-06-29 | 2012-06-19 | Innocom Technology (Shenzhen) Co., Ltd. | Display device with height-adjustment assembly having spring member |
-
2003
- 2003-10-31 KR KR1020030076590A patent/KR100575620B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100827435B1 (en) * | 2006-01-31 | 2008-05-06 | 삼성전자주식회사 | Method of fabricating gate with oxygen free ashing process in semiconductor device |
| US8201784B2 (en) * | 2007-06-29 | 2012-06-19 | Innocom Technology (Shenzhen) Co., Ltd. | Display device with height-adjustment assembly having spring member |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100575620B1 (en) | 2006-05-03 |
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