KR920010425B1 - 전극의 접속방법 - Google Patents

전극의 접속방법 Download PDF

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KR920010425B1
KR920010425B1 KR1019880016785A KR880016785A KR920010425B1 KR 920010425 B1 KR920010425 B1 KR 920010425B1 KR 1019880016785 A KR1019880016785 A KR 1019880016785A KR 880016785 A KR880016785 A KR 880016785A KR 920010425 B1 KR920010425 B1 KR 920010425B1
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electrode
semiconductor element
resin
circuit board
electrodes
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KR890011039A (ko
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겐죠 하다다
히로아끼 후지모도
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마쯔시다멘기산교 가부시기가이샤
다니이 아끼오
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Abstract

내용 없음.

Description

전극의 접속방법
제1도는 종래 기술에 있어서의 절연수지로 접속된 반도체소자의 단면도.
제2도는 본 발명의 일실시예의 접속공정을 도시한 단면도.
* 도면의 주요부분에 대한 부호의 설명
1 : 반도체소자 2 : 반도체소자의 전극
3 : 회로기판 4 : 회로기판의 전극
5 : 가압공구 6 : 절연수지
6a : 반도체소자의 주위영역 6b : 전극의 인접부
7 : 금속범프 12,13 :자외선
본 발명은 전극의 접속방법에 관한 것으로, 특히, 반도체소자를 페이스다운(face down)방식으로, 절연수지를 사용하여 접속하는 방법에 관한 것이다.
회로기판상에 반도체소자를 페이스다운 접속하는 방법에 관해서는, 반도체소자의 전극 상에 땜납 범프를 형성하여 회로기판상의 배선전극과 결합시키는 방법이 공지되어 있다. 이 방법에서, 반도체소자의 전극과 회로기판의 전극은 땜납 범프에 의해 고정되므로, 반도체소자 또는 회로기판상에 열 또는 기계적 응력이 작용하면, 이 응력은 땜납 범프의 접합부상에 전체적으로 집중되어 접합부의 파손을 발생시키므로 신뢰성을 저하시킨다.
이들 문제점을 해결하기 위해서, 제1도에 도시한 바와 같이, 반도체소자(1)상에 전극(2)을 배치하고, 이 전극(2)과 회로기판(3)의 배선전극(4)을 위치맞춤하고, 반도체소자(1)와 회로기판(3)사이에 절연수지를 삽입하고, 반도체소자(1)를 가압하면 상기 절연주지를 경화시킨다. 경화시 절연수지의 수지의 수축력을 이용하여 반도체소자(1)의 전극(2)을 회로 기판(2)의 배선전극(4)에 대해 압착시킴으로써, 전기접속을 얻는다.
(예를 들면, 미국특허 제4,749,120호).
제1도에 도시한 종래의 제조방법에서, 반도체소자(1)의 전극(2)과 회로기판(3)의 전극(4)사이에 절연영역이 배치되며, 이들은 함께 직접 가압되어 수지를 경화시킨다. 따라서, 두전극(2),(4)사이에 개입되어 있는 수지를 제거하지 않으면 두 전극의 전기접속은 얻을 수 없으므로, 반도체소자나 회로기판은 고압으로 압착된다. 그 결과, 반도체소자나 회로기판상에 휨응력이 형성되어 전극사이의 접속은 부분적으로 손상되어 바람직한 접속을 얻기 어렵다. 또한, 압력이 높을 때 반도체소자를 파괴할 위험이 있으며, 특히 이것은 Si 이외에 GaAs같은 깨지기 쉬운 소자에서 명백하다.
더욱이, 절연수지는 반도체소자(1)의 전체표면상에 도포되므로 반도체소자나, 외로기판을 가열하여 온도를 상승시킬 때, 전체절연수지는 반도체소자(1)의 전체표면상에 도포되므로 반도체소자나, 회로기판을 가열하여 온도를 상승시킬 때, 전체절연수지는 팽창되고, 이 팽창력이 수축력을 초과할 때, 압착부준에서의 전극과 배선전 극은 서로 분리되어 종종 접합부에 결함을 발생시킨다.
그러므로, 본 발명의 주목적은 절연수지를 사용하여 반도체소자를 페이스다운 방식으로 접속시킬 때, 반도체소자에 대한 손상이 없고 접속시 압착력이 적은, 고신뢰성의 접속방법을 제공하는데 있다.
본 발명의 다른 목적은 반도체소자의 전극과 회로기판의 전극사이에 절연수지를 삽입하지 않고 접속시켜, 이들 전극사이의 접속저항을 현저하게 낮추는 접속방법을 제공하는데 있다.
본 발명의 또 다른 목적은 반도체소자와 회로기판사이의 수지개입량을 최소화하여, 수지의 열 팽창에 기인한 전극사이의 접합불량 발생없이 고 신뢰성의 접속을 얻도록 하는 접속방법을 제공하는데 있다.
이들 및 기타 목적을 성취하기 위해서, 본 발명은 반도체소자의 전극과 회로기판의 전극을 위치맞춤하고, 안전한 접속을 얻기 위해 앙쪽을 압착하고, 반도체소자의 주위 가장자리에 절연수지를 적하하여 주입하고, 수지를 경화시키고, 전극 사이의 안전한 접속을 얻기 위해 압력을 제거하는 단계를 포함하는 전극의 접속방법을 제공한다.
본 발명의 방법에 따라서, 반도체소자의 전극과, 회로기판의 전극을 압착한후에 수지를 적하, 주입하므로, 전극사이의 수지개입과 수지의 열팽창과 같은 상기 언급된 문제점은 해결된다.
이하, 제2도와 관련하여 본 발명의 실시예를 설명한다. 우선, 반도체집적회로소자등의 반도체소자(1)의 전극(2)과 회로기판(3)의 전극(4)을 위치맞춤하고 (제2a도), 가압공구(5)로 전극(2)과 (4)사이에 압력을 가하여 서로 접촉시키고, 최소한 반도체소자(1)와 회로기판(3)사이의 틈으로 반도체소자의 특면으로부터 광경화성절연수지(6)을 주입한다. 실제적으로, 반도체소자(1)의 주위 가장자리를 따라 분배기와 같은 도구(10)를 사용하여 수지를 붓는다.(제2b도).
그후 광경화성절연수지()를 경화시키는 파장을 지닌 광(40 mw/cm2에서, 대략 10~30초)을 조사한다. 예를 들면, 자외선경화형 수지의 경우에, 회로기판의 측면 또는 반도체소자의 측면으로부터 자외선(12),(13)를 조사하여 광경화성수지(6)를 경화시킨다.(제2도(C)). 이런 광경 화를 시키기 직전에, 더욱 가압상태를 형성하는 것도 가능하며, 예를 들면, 수지(6)의 주입시 전극당 5g의 압력을 가하고, 조사시10~70g의 압력을 가하며, 경화후에는, 이 압력을 제거한다.(제2d도). 그 결과, 전극(2),(4)은 서로 전기접속되고 동시에 반도체소자(1)와 회로기판(3)은 수지(6)에 의해 서로 접착고정 된다. 반도체소자의 전극(2)은 예를 들면, 5~20㎛의 Au범프(7)이며, 이 범프를 회로기판의 전극(4)상에 형성해도 된다.
경화후 광경화성수지(6)의 상태가 제2d도에 도시한 바와 같이 회소한 반도체소자(1)의 주위영역(6a)과 전극(2),(4)의 인접부(6b)에 존재한다.
광경화성수지(6)로서는, 빛에 의해서만 경화되는 아크릴계 또는 에폭시계수지를 사용해도 되며, 또한 빛, 열에 모두 경화되는 수지를 사용해도 된다. 예를 들면, 회로기판이 불투명한 경우에는, 가입상태에서 반도체 소자의 배면 쪽으로부터 광을 조사하여 반도체소자 주위의 수지를 경화시키고, 전극 근처의 광이 조사되지 않았던 수지는 상온 또는 열에 의해 경화시킬 수 있다.
이하, 실제 실험결과를 설명한다.
견본은 7㎜ 평방의 Si 칩위에 100㎛의 간격으로 형성된 3000개의 Au전극(2)을 지니는 반도체소자(1)로서, Au전극(2)의 높이는 5㎛이며, 회로기판(3)은 글래스판이고, 배선전극(4)은 Cr-Au로 구성되어 있다. 실험은 열응력에 가장 민감한 열충격실험으로, -55℃/+150℃의 조건하에 실행하였다.
그 결과, 제1도에 도시한 종래의 방법에서는, 520사이클에서 접합불량이 발생되었으나, 본 발명의 방법에 의한 구성(제2d도)에서는 2500사이클 후에도 불량은 발생되지 않았다.
그러므로 본 발명의 구성은 열응력에 대해서 매우 효과적이다.
또한, 100㎛2의 전극 사이의 접촉영역에서 종래 기술은 초기접속점에 있어서의 접촉저항이 4~10mΩ인 반면 본 발명은 한자리 숫자이상 작은 0.2~0.6mΩ이며, 더욱이, 1200개의 LSI 칩의 접속결과, 접속시 LSI칩 파괴비율은 종래 기술에서 0.35%이었으나, 본 발명에서는 거의 0%이었다.
또한, 본 발명은 반도체소자의 접속뿐 아니라 전극을 지니는 두 회로기판의 접속에도 적용될 수 있다.
특히, 본 발명은 다음의 이점을 지닌다.
본 발명의 방법에 의하면, 절연수지는 가압 상태에서 적하, 주입되므로, 수지는 반도체소자의 전극과 회로기판의 전극사이에 개입되지 않아 전극사이의 접촉저항은 극별히 감소된다.
2. 또한, 수지는 가압 상태에서 적하되므로, 필요한 압력은 종래 기술에 대해 대략1/3~1/2이다. 그러므로, 반도체소자에 가해진 압력이 작아 반도체소자는 파손되지 않으며, 본 발명은 Si 이외에도 GaAs 및 InP와 같은 깨지기 쉬운 화합물로 구성된 반도체소자에도 적용할 수 있다.
3. 본 발명의 제조방법에서, 절연수지는 반도체소자의 주위와 전극근처에만 존재하므로, 수지를 팽창하는 힘이 작아, 결함된 전극을 떼어놓는 힘이 적기 때문에 높은 신뢰성을 얻을 수 있다.
4. 수지는 전극을 함께 압착한 후에 주입되므로, 반도체소자의 특성은 가압상태 에서 측정될 수 있으며, 반도체소자가 불량인 경우 쉽게 교환될 수 있으며, 또한, 수지가 회로기판 상에 퇴적되지 않아 교환에 필요한 공정수가 현저히 단축된다.
5. 주입된 수지는 반도체소자의 주위와 전극 근처에 존재하므로, 회로기판이 불투명한 경우, 반도체소자의 배면 쪽으로부터 광을 조사하면, 배면주위를 선회하는 광을 이용하여 전체의 수지를 경화시킬 수 있다.

Claims (4)

  1. 제1기판 상에 형성된 전극과 제2기판 상에 형성된 전극을 위치 맞춤하는 단계와, 상기 두 전극을 함께 압착하는 단계와, 상기 제1기판 또는 제2기판의 측면으로부터 절연수지를 주입하는 단계와, 수지를 경화시킨 후 압력을 제거하는 단계를 포함하는 것을 특징으로 하는 전극의 접속방법.
  2. 제1항에 있어서, 제1기판은 반도체칩이며, 제2기판은 배선기판인 것을 특징으로 하는 전극의 접속 방법.
  3. 제1항에 있어서, 제1기판 또는 제2기판의 전극은 금속범프로 구성되어 있는 것을 특징으로 하는 전극의 접속방법.
  4. 제1항에 있어서, 절연수지는 빛 또는 열에 의해 경화되는 것을 특징으로 하는 전극의 접속방법.
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