JP2547895B2 - 半導体装置の実装方法 - Google Patents

半導体装置の実装方法

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Publication number
JP2547895B2
JP2547895B2 JP2274650A JP27465090A JP2547895B2 JP 2547895 B2 JP2547895 B2 JP 2547895B2 JP 2274650 A JP2274650 A JP 2274650A JP 27465090 A JP27465090 A JP 27465090A JP 2547895 B2 JP2547895 B2 JP 2547895B2
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
electrode
photo
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2274650A
Other languages
English (en)
Other versions
JPH03290936A (ja
Inventor
圭司 山村
孝 貫井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to KR1019910004086A priority Critical patent/KR940010537B1/ko
Priority to DE69102919T priority patent/DE69102919T2/de
Priority to EP91302413A priority patent/EP0449496B1/en
Publication of JPH03290936A publication Critical patent/JPH03290936A/ja
Priority to US07/944,008 priority patent/US5296063A/en
Application granted granted Critical
Publication of JP2547895B2 publication Critical patent/JP2547895B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Description

【発明の詳細な説明】 （イ）産業上の利用分野 この発明は、半導体装置を回路基板上に光硬化性接着
剤を用いて実装する半導体装置の実装方法に関する。
（ロ）従来の技術 半導体装置の電極と回路基板の電極とを対向させた、
いわゆるフェイスダウン状態で、加圧接続し、光硬化性
接着剤により固定する半導体装置の実装方法は、加熱工
程を必要としないため半導体装置や回路基板に熱的損傷
を与えることがない。電極間の接続を圧接により行うた
め半田付けなどのように電極材料を金属接合が可能な材
料に限定する必要がない。工程が単純かつスピーディー
である等の利点を有する。
従来、この光硬化性接着剤を用いた圧接による半導体
装置の実装方法としては、半導体装置の回路基板との接
続面又は回路基板の半導体装置との接続面に光硬化性接
着剤を塗布後、半導体装置と回路基板を対向して加圧し
て対応する位置の電極を電気的に導通させ、この状態で
光硬化性接着剤を硬化させることにより実装する手法が
用いられている（たとえば特開平２−23623号公報参
照）。
（ハ）発明が解決しようとする課題 ところで、従来のこのような実装方法では、実装後の
電気テストで半導体装置の不良や半導体装置と回路基板
間の接続不良が確認され半導体装置を交替する必要が生
じた場合には、半導体装置と回路基板との間に外力を作
用させることにより、接続面の光硬化性接着剤の硬化物
を破断させて半導体装置を回路基板から除し、新たな半
導体装置を再実装するようにしている。しかしながら、
この場合、光硬化性接着剤の硬化物が回路基板電極上に
残存するため、これを完全に除去した後でなければ新た
な半導体装置を実装できないという問題点があった。
この発明は、このような事情を考慮してなされたもの
で、回路基板上に残存する光硬化性接着剤を除去する作
業を必要とすることなく、新たな半導体装置を回路基板
上に再実装することが可能な実装方法を提供するもので
ある。
（ニ）課題を解決するための手段 この発明は、下面の周縁部に接続用電極が形成された
半導体装置を回路基板上面に固着し、半導体装置の接続
用電極を回路基板の回路電極に接触させて接続する半導
体装置の実装方法において、（１）半導体装置の下面お
よび回路基板の上面の少くともいずれか一方に光硬化接
着剤を塗布する工程と、（２）上記半導体装置と回路基
板を対向させて互いに対応する位置の接続用電極と回路
電極とを位置合わせする工程と、（３）半導体装置の下
面中央部の一部に存在する光硬化性接着剤のみを硬化さ
せて仮り付けする工程と、（４）半導体装置と回路基板
との接続の良・不良を電気的に評価する工程と、（５）
半導体装置の回路基板との接続が不良と評価されたと
き、前記硬化部分にせん断力を加えて半導体装置を回路
基板から除去し、上記（１）〜（３）の工程を実行して
新たな半導体装置を回路基板に固定する工程と、（６）
半導体装置と回路基板との接続が良と評価されたとき、
上記光硬化性接着剤の未硬化部を硬化させる工程からな
ることを特徴とする半導体装置の実装方法である。
（ホ）作用 この半導体装置の実装方法においては、先ず、半導体
装置の回路基板との接続面又は回路基板の半導体装置と
の接続面に光硬化性接着剤を塗布する。次に、この半導
体装置と回路基板を対向して加圧して対応する位置の電
極を位置合せする。そして、半導体装置と回路基板の界
面に存在する光硬化性接着剤の内、半導体装置の電極上
に存在しない光硬化性接着剤を部分的に硬化する。次
に、この状態で電気テストを行い、その後、光硬化性接
着剤の未硬化部を硬化する。したがって、電気テストに
より半導体装置の不良や半導体装置と回路基板の接続不
良が確認されたときに、交換のため半導体装置を除去し
ても、回路基板の電極上の光硬化性接着剤は未硬化状態
であるためこの部分に光硬化性接着剤を補充するだけで
新たな半導体装置を再実装することができる。
（ヘ）実施例 以下、図面に示す第１および第２の実施例に基づいて
この発明を詳述する。これによってこの発明が限定され
るものではない。
［第１の実施例］ 第１図は半導体装置13を回路基板16上に実装した場合
の構成を示す断面図である。半導体装置13はシリコンあ
るいはガリウムヒ素などの基材より成り、その一方表面
には図示しない多数のトランジスタやダイオードなどか
ら成る集積回路が形成されており、その周辺部には回路
基板16上の接続用電極17と接続される電極14が形成され
ている。また、この電極14上には接続用部材として導電
性粒子15が配置されている（導電性粒子15の詳細につい
ては、特開平２−23623号広報参照）。また、回路基板1
6はガラスなどの透光性基材より成り、その一方表面に
は、前記電極14に対応する位置に対応した大きさで電極
17が形成されており、この電極17は回路基板16上に形成
された電気テスト用電極19と配線18により接続されてい
る。半導体装置13の電極14は回路基板16の電極17と導電
性粒子15を介して圧接により電気的に接続されており、
この状態で、半導体装置13が回路基板16上に光硬化性接
着剤（たとえば、日本ロックタイト（株）製のNo.350）
20により固定されている。
次に、第２図（１）〜第２図（４）を参照して、第１
図に示す半導体装置の実装方法について説明する。
先ず、第２図（１）に示されるように、回路基板16の
半導体装置13実装領域上に、印刷、転写、あるいはディ
スペンサーによる滴下などの方法によって、未硬化状態
の光硬化性接着剤層20aを形成する。
次に、第２図（２）に示されるように、半導体装置13
を回路基板16上に、電極14と電極17が対向するように設
置して加圧する。
次に、第２図（３）に示されるように、半導体装置13
と回路基板16の間に存在する光硬化性接着剤層の内、半
導体装置13の電極14の存在しない領域、例えばこの場合
に於いては中央部の領域の光硬化性接着剤層20bのみを
光硬化性接着剤の硬化波長を有する光を照射することに
より硬化させる。これにより、加圧を除去した後にも半
導体装置13の電極14と回路基板16の電極17は電気的に接
続され、かつ電極部の光硬化性接着剤は未硬化状態で保
持される。
次に、加圧を除去後、回路基板16上に形成された電気
テスト用電極19を介して半導体装置13の電気テストを行
う。
この電気テストにて良好な結果が得られた場合には、
第２図（４）に示されるように、回路基板16を介して光
硬化性接着剤層20の全領域に光硬化性接着剤の硬化波長
を有する光を照射することにより未硬化部の光硬化性接
着剤を硬化し、実装が完了する。この場合、回路基板16
を裏面から通過した光は半導体装置13に反射して散乱
し、電極17の光硬化性接着剤層20を硬化させるので、電
極17は必ずしも透明電極である必要はない。
一方、電気テストにて不良が確認された場合には、実
装した半導体装置13を除去し、再度新たに別の半導体装
置を実装する必要がある。
次に、上記のように実装した半導体装置の交換方法に
ついて第３図（１）〜第３図（３）を用いて説明する。
先ず、第３図（１）に示されるように、回路基板16上に
実装された半導体装置13にせん断力Ｆを作用させる。そ
れにより第３図（２）に示されるように半導体装置13が
回路基板16上から除去される。この作業は回路基板16を
加熱した状態で行えば、光硬化性接着剤20の強度がその
加熱により低下するため、より小さい力で行うことがで
きる。この場合の加熱温度は、光硬化性接着剤の物性に
依存するが100℃〜200℃とすることが望ましい。この状
態で、第３図（２）に示すように、回路基板16上におい
て、半導体装置実装領域の接続用電極17のない中央部に
光硬化性接着剤の硬化物20bが存在するが、電極17を含
む周辺部の光硬化性接着剤20aは未硬化のままである。
次に、この回路基板16の半導体装置実装領域上に、新
たに光硬化性接着剤をディスペンサーによる滴下等の方
法で補充し、前述の半導体装置の実装方法に準じて新た
な半導体装置13aの実装を行う（第３図（３）参照）。
［第２の実施例］ 第４図は半導体装置113を回路基板116上に実装した場
合の構成を示す断面図である。半導体装置113はシリコ
ンあるいはガリウムヒ素などの基材より成り、その表面
には図示しない多数のトランジスタやダイオードなどか
ら成る集積回路が形成されており、その周辺部には、回
路基板116上の接続用電極117と接続される突起電極114
が形成されている。また、回路基板116はガラスなどの
透光性基板より成り、その表面には、前記突起電極114
に対応する位置に対応した大きさで電極117が形成され
ており、この電極117は回路基板116上に形成された電気
ラスト用電極119と配線118により接続されている。半導
体装置113の突起電極114は回路基板116の電極117と圧接
により電気的に接続されており、この状態で、半導体装
置113が回路基板116上に光硬化性接着剤120により固定
されている。
次に、第５図（１）〜第５図（４）を参照して、第４
図に示す半導体装置の実装方法について説明する。
先ず、第５図（１）に示されるように、半導体装置11
3の突起電極114の形成面側に、印刷、転写あるいはディ
スペンサーによる滴下などの方法によって、未硬化状態
の光硬化性接着剤層120aを形成する。
次に、第５図（２）に示されるように、半導体装置11
3を回路基板116上に突起電極114と電極117が対向するよ
うに位置合せして設置する。
次に、第５図（３）に示されるように、半導体装置11
3と回路基116の間に存在する光硬化性接着剤層の内、半
導体装置113の突起電極114の存在しない領域、例えば、
この場合に於いては中央部の領域の一部の光硬化性接着
剤120bのみを光硬化性接着剤の硬化波長を有する光を照
射し、硬化させることにより、半導体装置113を回路基
板116上に仮固定する。なお、この状態では半導体装置1
13の突起電極114と回路基板116の電極117とはかならず
しも電気的に接続されていなくともかまわない。
次に、半導体装置113を回路基板116上に加圧すること
により半導体装置113の突起電極114と回路基板116の電
極117とを電気的に接続し、この状態で、回路基板116上
に形成された電気テスト用電極119を介して半導体装置1
13の電気テストを行う。
この電気テストにて良好な結果が得られた場合には、
第５図（４）に示されるように、半導体装置113を回路
基板116上に加圧したままの状態で回路基板116を介して
光硬化性接着剤層120の全領域に光硬化性接着剤の硬化
波長を有する光を照射することにより未硬化部の光硬化
性接着剤を硬化し、実装が完了する。
また、電気テストにて不良が確認された場合には、第
１の実施例と同様に、半導体装置113を除去後、再度新
たに別の半導体装置を本半導体装置の実装方法に準じて
実装する。
上記実施例においては、導電性弾性粒子を電極上に配
置して半導体装置を回路基板上に実装する場合及び金属
突起電極を有する半導体装置を回路基板上に実装する場
合について説明したが、半導体装置の電極の接続構造は
これに限定する必要はなく、光硬化性接着剤を用いた圧
接により実装が可能な全ての半導体装置にこの発明が適
用できることはいうまでもない。
（ト）発明の効果 この発明によれば、半導体装置と回路基板との接続面
に存在する光硬化性接着剤の内、電極の存在しない中央
部の領域の光硬化性接着剤のみを硬化した後電気テスト
を行うため、電気テストにより半導体装置の不良や半導
体装置と回路基板の接続不良が確認され、半導体装置を
交換する必要が生じた場合にも、回路基板上に存在する
光硬化性接着剤を除去することなく容易に新たな半導体
装置を再実装することができる。
【図面の簡単な説明】
第１図はこの発明の第１の実施例によって半導体装置を
回路基板上に実装した構造を示す説明図、第２図（１）
〜第２図（４）はこの発明の第１の実施例の実装工程を
示す説明図、第３図（１）〜第３図（３）は実装した半
導体装置の交換方法を示す説明図、第４図はこの発明の
第２の実施例の第１図対応図、第５図（１）〜第５図
（４）はこの発明の第２の実施例の実装工程説明図であ
る。 13,13a……半導体装置、 16……回路基板、 14,17,19……電極、 15……導電性粒子、 20,20a,20b……光硬化性接着剤。
フロントページの続き (56)参考文献 特開 平２−44742（ＪＰ，Ａ) 特開 平２−22834（ＪＰ，Ａ) 特開 平２−62066（ＪＰ，Ａ) 特開 平３−195033（ＪＰ，Ａ) 特開 平３−129843（ＪＰ，Ａ) 特開 平２−209741（ＪＰ，Ａ) 特開 平２−82633（ＪＰ，Ａ)

Claims (1)

    (57)【特許請求の範囲】
  1. 【請求項１】下面の周縁部に接続用電極が形成された半
    導体装置を回路基板上面に固着し、半導体装置の接続用
    電極を回路基板の回路電極に接触させて接続する半導体
    装置の実装方法において、 （１）半導体装置の下面および回路基板の上面の少くと
    もいずれか一方の光硬化接着剤を塗布する工程と、 （２）上記半導体装置と回路基板を対向させて互いに対
    応する位置の接続用電極と回路電極とを位置合わせする
    工程と、 （３）半導体装置の下面中央部の一部に存在する光硬化
    性接着剤のみを硬化させて仮り付けする工程と、 （４）半導体装置と回路基板との接続の良・不良を電気
    的に評価する工程と、 （５）半導体装置の回路基板との接続が不良と評価され
    たとき、前記硬化部分にせん断力を加えて半導体装置を
    回路基板から除去し、上記（１）〜（３）の工程を実行
    して新たな半導体装置を回路基板に固定する工程と、 （６）半導体装置と回路基板との接続が良と評価された
    とき、上記光硬化性接着剤の未硬化部を硬化させる工程 からなること特徴とする半導体装置の実装方法。
JP2274650A 1990-03-20 1990-10-12 半導体装置の実装方法 Expired - Fee Related JP2547895B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019910004086A KR940010537B1 (ko) 1990-03-20 1991-03-14 반도체 소자를 설치하는 방법
DE69102919T DE69102919T2 (de) 1990-03-20 1991-03-20 Verfahren zur Montage von einer Halbleiteranordnung.
EP91302413A EP0449496B1 (en) 1990-03-20 1991-03-20 Method for mounting a semiconductor device
US07/944,008 US5296063A (en) 1990-03-20 1992-09-11 Method for mounting a semiconductor device

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KR910017615A (ko) 1991-11-05
KR940010537B1 (ko) 1994-10-24
JPH03290936A (ja) 1991-12-20

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