JPH03290936A - 半導体装置の実装方法 - Google Patents

半導体装置の実装方法

Info

Publication number
JPH03290936A
JPH03290936A JP2274650A JP27465090A JPH03290936A JP H03290936 A JPH03290936 A JP H03290936A JP 2274650 A JP2274650 A JP 2274650A JP 27465090 A JP27465090 A JP 27465090A JP H03290936 A JPH03290936 A JP H03290936A
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
electrodes
photocurable adhesive
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2274650A
Other languages
English (en)
Other versions
JP2547895B2 (ja
Inventor
Keiji Yamamura
山村 圭司
Takashi Nukui
貫井 孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to KR1019910004086A priority Critical patent/KR940010537B1/ko
Priority to EP91302413A priority patent/EP0449496B1/en
Priority to DE69102919T priority patent/DE69102919T2/de
Publication of JPH03290936A publication Critical patent/JPH03290936A/ja
Priority to US07/944,008 priority patent/US5296063A/en
Application granted granted Critical
Publication of JP2547895B2 publication Critical patent/JP2547895B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明は、半導体装置を回路基板上に光硬化性接着剤
を用いて実装する半導体装置の実装方法に関する。
(ロ)従来の技術 半導体装置の電極と回路基板の電極とを対向させた、い
わゆるフェイスダウン状聾で、加圧接続し、光硬化性接
着剤により固定する半導体装置の実装方法は、加熱工程
を必要としないため半導体装置や回路基板に熱的損傷を
与えることかだい電極間の接続を圧接により行うため半
田(”!’ ft riとのように電極材料を金属接合
が可能な材料に限定する必要がない、工程が単純かつス
ピーデイ−である等の利点を有する。
従来、この光硬化性接着剤を用いた圧接による半導体装
置の実装方法としては、半導体装置の回路基板との接続
面又は回路基板の半導体装置との接続面に光硬化性接着
剤を塗布後、半導体装置と回路基板を対向して加圧して
対応する位置の電極を電気的?こ導通させ、この状態で
光硬化性接着剤を硬化させることにより実装する手法が
用いられている(たとえば特開平2−23623号公報
参照)、。
(ハ)発明が解決しようとする課題 ところで、従来のこのような実装方法では、実装後の電
気テストで半導体装置の不良や半導体装置と回路基板間
の接続不良が確認され半導体装置を交替する必要が生じ
た場合には、半導体装置と回路基板との間に外力を作用
させることにより、接続面の光硬化性接着剤の硬化物を
破断させて半導体装置を回路基板から除し、新たな半導
体装置を再実装するようにしている。しかしながら、こ
の場合、光硬化性接着剤の硬化物が回路基板電極上に残
存するため、これを完全に除去した後でなければ新たな
半導体装置を実装できないという問題点があった。
この発明は、このような事情を考慮してなされたもので
、回路基板上に残存する光硬化性接着剤を除去する作業
を必要とすることなく、新たな半導体装置を回路基板上
に再実装することが可能な実装方法を提供するものであ
る。
(ニ)課題を解決するための手段 この発明は、接続用電極が形成された半導体装置を、こ
の半導体装置の電極と対応する位置に電極が形成された
回路基板に接続する半導体装置の実装方法において、半
導体装置の回路基板との接続面又は回路基板の半導体装
置との接続面に光硬化接着剤を塗布する工程と、上記半
導体装置と回路基板を対向させて互いに対応する位置の
電極を位置合せする工程と、前記電極以外の部分に存在
する光硬化性接着剤を部分的に硬化させる工程と、半導
体装置と回路基板との接続を電気的に評価する工程と、
上記光硬化性接着剤の未硬化部を硬化させる工程からな
ることを特徴とする半導体装置の実装方法である。
(ホ)作用 この半導体装置の実装方法においては、先ず、半導体装
置の回路基板との接続面又は回路基板の半導体装置との
接続面に光硬化性接着剤を塗布する。次に、この半導体
装置と回路基板を対向して加圧して対応する位置の電極
を位置合せする。そして、半導体装置と回路基板の界面
に存在する光硬化性接着剤の内、半導体装置の電極上に
存在しない光硬化性接着剤を部分的に硬化する。次に、
この状態で電気テストを行い、その後、光硬化性接着剤
の未硬化部を硬化する。したがって、電気テストにより
半導体装置の不良や半導体装置と回路基板の接続不良が
確認されたときに、交換のため半導体装置を除去しても
、回路基板の電極上の光硬化性接着剤は未硬化状態であ
るためこの部分に光硬化性接着剤を補充するだけで新た
な半導体装置を再実装することができる。
(へ)実施例 以下、図面に示す第1および第2の実施例に基づいてこ
の発明を詳述する。これによってこの発明が限定される
ものではない。
[第1の実施例] 第1図は半導体装置13を回路基板16上に実装した場
合の構成を示す断面図である。半導体装置13はシリコ
ンあるいはガリウムヒ素などの基材より成り、その一方
表面には図示しない多数のトランジスタやダイオードな
どから戊る集積回路が形成されており、その周辺部には
回路基板16上の接続用電極17と接続される電極14
が形成されている。また、この電極I4上には接続用部
材として導電性粒子15が配置されている(導電性粒子
15の詳細については、特開平2−23g23号公報参
照)。また、回路基板16はガラスなどの透光性基材よ
り成り、その一方表面には、前記電極!4に対応する位
置に対応した大きさで電極17か形成されており、この
電極17は回路基板16上に形成された電気テスト用電
極19と配線18により接続されている。半導体装置1
3の電極14は回路基板16の電極17と導電性粒子1
5を介して圧接により電気的に接続されており、この状
態で、半導体装置13が回路基板16上に光硬化性接着
剤(たとえば、日本ロックタイト(株)製のNo、35
0) 20により固定されている。
次に、第2図(1)〜第2図(4)を参照して、第1図
に示す半導体装置の実装方法について説明する。
先ず、第2図(1)に示されるように、回路基板16の
半導体装置13実装領域上に、印刷、転写、あるいはデ
イスペンサーによる滴下などの方法によって、未硬化状
態の光硬化性接着剤層20aを形成する。
次に、第2図(2)に示されるように、半導体装置!3
を回路基板16上に、電極14と電極17が対向するよ
うに設置して加圧する。
次に、第2図(3)に示されるように、半導体装置13
と回路基板16の間に存在する光硬化性接着剤層の内、
半導体装置13の電極14の存在しない領域、例えばこ
の場合に於いては中央部の領域の光硬化性接着剤層20
bのみを光硬化性接着剤の硬化波長を有する光を照射す
ることにより硬化させる。これにより、加圧を除去した
後にも半導体装置13の電極14と回路基板16の電極
17は電気的に接続され、かつ電極部の光硬化性接着剤
は未硬化状態で保持される。
次に、加圧を除去後、回路基板16上に形成された電気
テスト用電極19を介して半導体装置13の電気テスト
を行う。
この電気テストにて良好な結果が得られた場合には、第
2図(4)に示されるように、回路基板I6を介して光
硬化性接着剤層20の全領域に光硬化性接着剤の硬化波
長を有する光を照射することにより未硬化部の光硬化性
接着剤を硬化し、実装が完了する。この場合、回路基板
16を裏面から通過した光は半導体装置13に反射して
散乱し、電極17の光硬化性接着剤層20を硬化させる
ので、電極17は必ずしも透明電極である必要はない。
一方、電気テストにて不良が確認された場合には、実装
した半導体装置13を除去し、再度新たに別の半導体装
置を実装する必要がある。
次に、上記のように実装した半導体装置の交換方法につ
いて第3図(1)〜第3図(3)を用いて説明する。先
ず、第3図(1)に示されるように、回路基板16上に
実装された半導体装置13にせん断力Fを作用させる。
それにより第3図(2)に示されるように半導体装置1
3が回路基板16上から除去される。この作業は回路基
板16を加熱した状態で行えば、光硬化性接着剤20の
強度がその加熱により低下するため、より/J)さい力
で行うことかできる。この場合の加勢温度は、光硬化性
接着剤の物性に依存するが100℃〜200℃とするこ
とが望ましい1.この状態で、第3図(2)に示すよう
に、回路基板16上において、半導体装置実装領域の接
続用電極17のない中央部に光硬化性接着剤の硬化物2
0bが存在するが、N極I7を含む周辺部の光硬化性接
着剤20aは未硬化のままである。
次に、この回路基板16の半導体装置実装領域上に、新
たに光硬化性接着剤をデイスペンサーによる廊下等の方
法で補充し、前述の半導体装置の実装方法に準じて新た
な半導体装置13aの実装を行う(第3図(3)参照)
[第2の実施例] 第4図は半導体装置113を回路基板116上に実装し
た場合の構成を示す断面図である。半導体装置113は
シリコンあるいはガリウムヒ累などの基材より成り、そ
の表面には図示しない多数のトランジスタやダイオード
などから成る集積回路が形成されており、その周辺部に
は、回路基板116上の接続用電極117と接続される
突起電極+14か形成されている。また、回路基板11
6はガラスなどの透光性基板より成り、その表面には、
前記突起電極+14に対応する位置に対応した大きさで
電極+17が形成されており、この電極+17は回路基
板116上に形成された電気ラスト用電極+19と配線
+18により接続さ右ている。半導体装置113の突起
電極114は回路基板116の電極+17と圧接により
電気的に接続されており、この状態で、半導体装置11
3が回路基板116上に光硬化性接着剤120により固
定されている。
次に、第5図(1)〜第5図(4)を参照して、第4図
に示す半導体装置の実装方法について説明する。
先ず、第5図(1)に示されるように、半導体装置+1
3の突起電極114の形成面側に、印刷、転写あるいは
デイスペンサーによる滴下などの方法によって、未硬化
状態の光硬化性接着剤層120aを形成する。
次に、第5図(2)に示されるように、半導体装置11
3を回路基板116上に突起電極114と電極117が
対向するように位置合せして設置する。
次に、第5図(3)に示されるように、半導体装置11
3と回路基板116の間に存在する光硬化性接着剤層の
内、半導体装置113の突起電極114の存在しない領
域、例えば、この場合に於いては中央部の領域の一部の
光硬化性接着剤120bのみを光硬化性接着剤の硬化波
長を有する光を照射し、硬化させることにより、半導体
装置113を回路基板116上に仮固定する。なお、こ
の状態では半導体装置113の突起電極114と回路基
板116の電極+17とはかならずしも電気的に接続さ
れていなくともかまわない。
次に、半導体装置113を回路基板116上に加圧する
ことにより半導体装置113の突起電極114と回路基
板116の電極117とを電気的に接続し、この状態で
、回路基板116上に形成された電気テスト用電極11
9を介して半導体装置113の電気テストを行う。
この電気テストにて良好な結果が得られた場合には、第
5図(4)に示されるように、半導体装置113を回路
基板116上に加圧したままの状態で回路基板116を
介して光硬化性接着剤層120の全領域に光硬化性接着
剤の硬化波長を有する光を照射することにより未硬化部
の光硬化性接着剤を硬化し、実装が完了する。
また、電気テストにて不良が確認された場合には、第1
の実施例と同様に、半導体装置113を除去後、再度新
たに別の半導体装置を本半導体装置の実装方法に準じて
実装する。
上記実施例においては、導電性弾性粒子を電極上に配置
して半導体装置を回路基板上に実装する場合及び金属突
起電極を有する半導体装置を回路基板上に実装する場合
について説明したが、半導体装置の電極の接続構造はこ
れに限定する必要はなく、光硬化性接着剤を用いた圧接
により実装が可能な全ての半導体装置にこの発明が適用
できることはいうまでもない。
(ト)発明の効果 この発明によれば、半導体装置と回路基板との接続面に
存在する光硬化性接着剤の内、電極の存在しない中央部
の領域の光硬化性接着剤のみを硬化した後電気テストを
行うため、電気テストにより半導体装置の不良や半導体
装置と回路基板の接続不良が確認され、半導体装置を交
換する必要が生じた場合にも、回路基板上に存在する光
硬化性接着剤を除去することなく容易に新たな半導体装
置を再実装することができる。
【図面の簡単な説明】
第1図はこの発明の第1の実施例によって半導体装置を
回路基板上に実装した構造を示す説明図、第2図(1)
〜第2図(4)はこの発明の第1の実施例の実装工程を
示す説明恥、第3図(1)〜第3図(3)は実装した半
導体装置の交換方法を示す説明図、第4図はこの発明の
第2の実施例の第1図対応図、第5図(1)〜第5図(
4)はこの発明の第2の実施例の実装工程説明図である
。 16・・・・・・回路基板、 14.17.19・・・・・電極、 15・・・・・・導電性粒子、 20.20a、20b・・・・・・光硬化性接着剤。 13.13a・・・・・・半導体装置、拳 1 閏 枦 閃 垣 阿 / /ノ 17 18 19 第 図 カoh 光密、射 光だ、鼾 閃 第 向 \ 20a

Claims (1)

    【特許請求の範囲】
  1. 1.接続用電極が形成された半導体装置を、この半導体
    装置の電極と対応する位置に電極が形成された回路基板
    に接続する半導体装置の実装方法において、半導体装置
    の回路基板との接続面又は回路基板の半導体装置との接
    続面に光硬化接着剤を塗布する工程と、上記半導体装置
    と回路基板を対向させて互いに対応する位置の電極を位
    置合せする工程と、前記電極以外の部分に存在する光硬
    化性接着剤を部分的に硬化させる工程と、半導体装置と
    回路基板との接続を電気的に評価する工程と、上記光硬
    化性接着剤の未硬化部を硬化させる工程からなることを
    特徴とする半導体装置の実装方法。
JP2274650A 1990-03-20 1990-10-12 半導体装置の実装方法 Expired - Fee Related JP2547895B2 (ja)

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KR1019910004086A KR940010537B1 (ko) 1990-03-20 1991-03-14 반도체 소자를 설치하는 방법
EP91302413A EP0449496B1 (en) 1990-03-20 1991-03-20 Method for mounting a semiconductor device
DE69102919T DE69102919T2 (de) 1990-03-20 1991-03-20 Verfahren zur Montage von einer Halbleiteranordnung.
US07/944,008 US5296063A (en) 1990-03-20 1992-09-11 Method for mounting a semiconductor device

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JP7029690 1990-03-20
JP2-70296 1990-03-20

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JPH03290936A true JPH03290936A (ja) 1991-12-20
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US5296063A (en) 1994-03-22

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