KR920010344B1 - 반도체 메모리 어레이의 구성방법 - Google Patents

반도체 메모리 어레이의 구성방법 Download PDF

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Publication number
KR920010344B1
KR920010344B1 KR1019890020108A KR890020108A KR920010344B1 KR 920010344 B1 KR920010344 B1 KR 920010344B1 KR 1019890020108 A KR1019890020108 A KR 1019890020108A KR 890020108 A KR890020108 A KR 890020108A KR 920010344 B1 KR920010344 B1 KR 920010344B1
Authority
KR
South Korea
Prior art keywords
word line
memory array
word lines
word
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
KR1019890020108A
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English (en)
Korean (ko)
Other versions
KR910013266A (ko
Inventor
서동일
조수인
민동선
김영래
Original Assignee
삼성전자주식회사
김광호
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사, 김광호 filed Critical 삼성전자주식회사
Priority to KR1019890020108A priority Critical patent/KR920010344B1/ko
Priority to JP2069926A priority patent/JPH0792998B2/ja
Priority to DE4009836A priority patent/DE4009836C2/de
Priority to GB9006756A priority patent/GB2239558B/en
Priority to FR9004026A priority patent/FR2656725B1/fr
Priority to US07/501,758 priority patent/US5097441A/en
Priority to IT48185A priority patent/IT1241520B/it
Priority to CN90106625A priority patent/CN1021996C/zh
Publication of KR910013266A publication Critical patent/KR910013266A/ko
Application granted granted Critical
Publication of KR920010344B1 publication Critical patent/KR920010344B1/ko
Expired legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/423—Shielding layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
KR1019890020108A 1989-12-29 1989-12-29 반도체 메모리 어레이의 구성방법 Expired KR920010344B1 (ko)

Priority Applications (8)

Application Number Priority Date Filing Date Title
KR1019890020108A KR920010344B1 (ko) 1989-12-29 1989-12-29 반도체 메모리 어레이의 구성방법
JP2069926A JPH0792998B2 (ja) 1989-12-29 1990-03-22 半導体メモリアレイ
GB9006756A GB2239558B (en) 1989-12-29 1990-03-27 Semiconductor memory device
DE4009836A DE4009836C2 (de) 1989-12-29 1990-03-27 Halbleiterspeichervorrichtung mit vermindertem Wortleitungskopplungsrauschen
FR9004026A FR2656725B1 (enExample) 1989-12-29 1990-03-29
US07/501,758 US5097441A (en) 1989-12-29 1990-03-30 Interdigitated and twisted word line structure for semiconductor memories
IT48185A IT1241520B (it) 1989-12-29 1990-07-31 "dispositivo di memoria a semiconduttori".
CN90106625A CN1021996C (zh) 1989-12-29 1990-07-31 半导体存储设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890020108A KR920010344B1 (ko) 1989-12-29 1989-12-29 반도체 메모리 어레이의 구성방법

Publications (2)

Publication Number Publication Date
KR910013266A KR910013266A (ko) 1991-08-08
KR920010344B1 true KR920010344B1 (ko) 1992-11-27

Family

ID=19294149

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890020108A Expired KR920010344B1 (ko) 1989-12-29 1989-12-29 반도체 메모리 어레이의 구성방법

Country Status (8)

Country Link
US (1) US5097441A (enExample)
JP (1) JPH0792998B2 (enExample)
KR (1) KR920010344B1 (enExample)
CN (1) CN1021996C (enExample)
DE (1) DE4009836C2 (enExample)
FR (1) FR2656725B1 (enExample)
GB (1) GB2239558B (enExample)
IT (1) IT1241520B (enExample)

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JPH0713864B2 (ja) * 1989-09-27 1995-02-15 東芝マイクロエレクトロニクス株式会社 半導体記憶装置
GB2246001B (en) * 1990-04-11 1994-06-15 Digital Equipment Corp Array architecture for high speed cache memory
JPH04271086A (ja) * 1991-02-27 1992-09-28 Nec Corp 半導体集積回路
KR940008722B1 (ko) * 1991-12-04 1994-09-26 삼성전자 주식회사 반도체 메모리 장치의 워드라인 드라이버 배열방법
EP0697735B1 (en) * 1994-08-15 2002-03-27 International Business Machines Corporation Single twist layout and method for paired line conductors of integrated circuits
KR0172376B1 (ko) * 1995-12-06 1999-03-30 김광호 서브워드라인 드라이버 구조를 가지는 반도체 메모리장치
US5793383A (en) * 1996-05-31 1998-08-11 Townsend And Townsend And Crew Llp Shared bootstrap circuit
US6034879A (en) * 1998-02-19 2000-03-07 University Of Pittsburgh Twisted line techniques for multi-gigabit dynamic random access memories
JP2000340766A (ja) * 1999-05-31 2000-12-08 Fujitsu Ltd 半導体記憶装置
US7259464B1 (en) 2000-05-09 2007-08-21 Micron Technology, Inc. Vertical twist scheme for high-density DRAMs
CA2342496A1 (en) 2001-03-30 2002-09-30 Atmos Corporation Twisted wordline straps
US6567329B2 (en) * 2001-08-28 2003-05-20 Intel Corporation Multiple word-line accessing and accessor
KR100541818B1 (ko) * 2003-12-18 2006-01-10 삼성전자주식회사 반도체 메모리 장치의 라인 배치구조
JP4564299B2 (ja) 2004-07-28 2010-10-20 株式会社東芝 半導体集積回路装置
KR100825525B1 (ko) * 2004-07-28 2008-04-25 가부시끼가이샤 도시바 반도체 집적 회로 장치
US7110319B2 (en) * 2004-08-27 2006-09-19 Micron Technology, Inc. Memory devices having reduced coupling noise between wordlines
JP4058045B2 (ja) * 2005-01-05 2008-03-05 株式会社東芝 半導体記憶装置
US20090154215A1 (en) * 2007-12-14 2009-06-18 Spansion Llc Reducing noise and disturbance between memory storage elements using angled wordlines
JP5612803B2 (ja) * 2007-12-25 2014-10-22 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体記憶装置
US7830221B2 (en) * 2008-01-25 2010-11-09 Micron Technology, Inc. Coupling cancellation scheme
JP6833873B2 (ja) 2016-05-17 2021-02-24 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 不揮発性メモリアレイを使用したディープラーニングニューラルネットワーク分類器
CN106097960B (zh) * 2016-06-16 2018-09-14 武汉华星光电技术有限公司 一种双边驱动装置及平板显示器
CN107622779B (zh) * 2017-10-30 2024-03-26 长鑫存储技术有限公司 一种存储阵列块及半导体存储器
US10803943B2 (en) 2017-11-29 2020-10-13 Silicon Storage Technology, Inc. Neural network classifier using array of four-gate non-volatile memory cells
US10699779B2 (en) 2017-11-29 2020-06-30 Silicon Storage Technology, Inc. Neural network classifier using array of two-gate non-volatile memory cells
US10748630B2 (en) 2017-11-29 2020-08-18 Silicon Storage Technology, Inc. High precision and highly efficient tuning mechanisms and algorithms for analog neuromorphic memory in artificial neural networks
US11087207B2 (en) 2018-03-14 2021-08-10 Silicon Storage Technology, Inc. Decoders for analog neural memory in deep learning artificial neural network
US10438636B2 (en) * 2017-12-07 2019-10-08 Advanced Micro Devices, Inc. Capacitive structure for memory write assist
US11893478B2 (en) 2019-01-18 2024-02-06 Silicon Storage Technology, Inc. Programmable output blocks for analog neural memory in a deep learning artificial neural network
US11500442B2 (en) 2019-01-18 2022-11-15 Silicon Storage Technology, Inc. System for converting neuron current into neuron current-based time pulses in an analog neural memory in a deep learning artificial neural network
US11023559B2 (en) 2019-01-25 2021-06-01 Microsemi Soc Corp. Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit
US10720217B1 (en) 2019-01-29 2020-07-21 Silicon Storage Technology, Inc. Memory device and method for varying program state separation based upon frequency of use
US11423979B2 (en) 2019-04-29 2022-08-23 Silicon Storage Technology, Inc. Decoding system and physical layout for analog neural memory in deep learning artificial neural network

Family Cites Families (12)

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Publication number Priority date Publication date Assignee Title
JPS57208691A (en) * 1981-06-15 1982-12-21 Mitsubishi Electric Corp Semiconductor memory
JPS6059677B2 (ja) * 1981-08-19 1985-12-26 富士通株式会社 半導体記憶装置
JPS59124092A (ja) * 1982-12-29 1984-07-18 Fujitsu Ltd メモリ装置
US4729119A (en) * 1984-05-21 1988-03-01 General Computer Corporation Apparatus and methods for processing data through a random access memory system
US4733374A (en) * 1985-03-30 1988-03-22 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device
CA1305255C (en) * 1986-08-25 1992-07-14 Joseph Lebowitz Marching interconnecting lines in semiconductor integrated circuits
JPS63153792A (ja) * 1986-12-17 1988-06-27 Sharp Corp 半導体メモリ装置
JPS63255898A (ja) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp 半導体記憶装置
JPH06105550B2 (ja) * 1987-07-08 1994-12-21 三菱電機株式会社 半導体記憶装置
JP2547615B2 (ja) * 1988-06-16 1996-10-23 三菱電機株式会社 読出専用半導体記憶装置および半導体記憶装置
JPH0713858B2 (ja) * 1988-08-30 1995-02-15 三菱電機株式会社 半導体記憶装置
JPH0713864B2 (ja) * 1989-09-27 1995-02-15 東芝マイクロエレクトロニクス株式会社 半導体記憶装置

Also Published As

Publication number Publication date
IT9048185A1 (it) 1992-01-31
DE4009836A1 (de) 1991-07-11
GB2239558A (en) 1991-07-03
FR2656725A1 (enExample) 1991-07-05
IT1241520B (it) 1994-01-17
US5097441A (en) 1992-03-17
GB9006756D0 (en) 1990-05-23
FR2656725B1 (enExample) 1994-11-04
DE4009836C2 (de) 1994-01-27
KR910013266A (ko) 1991-08-08
CN1052966A (zh) 1991-07-10
JPH0792998B2 (ja) 1995-10-09
IT9048185A0 (it) 1990-07-31
JPH03203085A (ja) 1991-09-04
CN1021996C (zh) 1993-09-01
GB2239558B (en) 1993-08-18

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