KR920008929A - 반도체 기억장치와 그 제조방법 - Google Patents

반도체 기억장치와 그 제조방법 Download PDF

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Publication number
KR920008929A
KR920008929A KR1019910019009A KR910019009A KR920008929A KR 920008929 A KR920008929 A KR 920008929A KR 1019910019009 A KR1019910019009 A KR 1019910019009A KR 910019009 A KR910019009 A KR 910019009A KR 920008929 A KR920008929 A KR 920008929A
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KR
South Korea
Prior art keywords
mos transistor
peripheral circuit
insulating film
forming
transistor region
Prior art date
Application number
KR1019910019009A
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English (en)
Inventor
다케아키 이시이
사토시 마에다
Original Assignee
아오이 죠이치
가부시끼가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아오이 죠이치, 가부시끼가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR920008929A publication Critical patent/KR920008929A/ko

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

내용 없음

Description

반도체 기억장치와 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예에 관한 반도체 기억장치를 나타내는 단면도,
제2도(a)-(d)는 본 발명의 반도체 기억장치의 제조방법을 나타내는 공정단면도.

Claims (2)

  1. 제1도전형 반도체 기판(100)상에 형성된 선택용 MOS 트랜지스터 및 정보 기억용 캐퍼시터로 구성되는 메모리셀과 이 메모리셀 주변에 형성된 MOS 트랜지스터로 이루어지는 주변회로를 구비하는 반도체 기억 장치에 있어서, 상기 선택용 MOS 트랜지스터의 게이트 산화막(106a)과 상기 주변 회로의 MOS 트랜지스터의 게이트 산화막(106b)은 각각의 막두께가 상이한 것을 특징으로 하는 반도체 기억장치.
  2. 제1도전형의 반도체 기판(100)상에 소자 분리 영역(101)을 형성하는 공정과, 이 공정 뒤에 상기 소자 분리 영역에 의하여 규정된 반도체 기판상에 제1의 절연막(102)를 형성하고, 이 제1의 절연막 상에 캐피시터 전극(103)을 형성하는 공정과, 이 공정 뒤에 상기 캐퍼시터 전극상 및 미리 정해진 선택용 MOS 트랜지스터 영역과 주변회로의 MOS 트랜지스터 영역에 제2의 절연막(104)을 형성하는 공정과, 이 공정 뒤에 상기 주변회로의 MOS 트랜지스터 영역의 상기 제2의 절연막을 제거하는 공정과, 이 공정 뒤에 상기 선택용 MOS 트랜지스터 영역과 주변회로의 MOS 트랜지스터 영역에 제3의 절연막(106)을 형성하는 공정과, 이 공정 뒤에 선택용 MOS 트랜지스트 영역과 주변회로의 MOS 트랜지스터 영역상에 동시에 게이트 전극(107,108)을 형성하는 공정을, 포함하는 것을 특징으로 하는 반도체 기억장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910019009A 1990-10-30 1991-10-29 반도체 기억장치와 그 제조방법 KR920008929A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP90-290844 1990-10-30
JP2290844A JPH04165670A (ja) 1990-10-30 1990-10-30 半導体記憶装置とその製造方法

Publications (1)

Publication Number Publication Date
KR920008929A true KR920008929A (ko) 1992-05-28

Family

ID=17761216

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910019009A KR920008929A (ko) 1990-10-30 1991-10-29 반도체 기억장치와 그 제조방법

Country Status (3)

Country Link
US (1) US5293336A (ko)
JP (1) JPH04165670A (ko)
KR (1) KR920008929A (ko)

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US5648281A (en) * 1992-09-21 1997-07-15 Siliconix Incorporated Method for forming an isolation structure and a bipolar transistor on a semiconductor substrate
KR0136935B1 (ko) * 1994-04-21 1998-04-24 문정환 메모리 소자의 제조방법
JP3261435B2 (ja) * 1995-01-19 2002-03-04 マイクロン・テクノロジー・インコーポレイテッド 周辺回路内にトランジスタを形成する方法
US5691217A (en) * 1996-01-03 1997-11-25 Micron Technology, Inc. Semiconductor processing method of forming a pair of field effect transistors having different thickness gate dielectric layers
JP4534163B2 (ja) * 1997-06-16 2010-09-01 エルピーダメモリ株式会社 半導体集積回路装置
KR19990008496A (ko) * 1997-07-01 1999-02-05 윤종용 복합 반도체 장치의 비대칭 게이트 산화막 제조 방법
JP3967440B2 (ja) * 1997-12-09 2007-08-29 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6066525A (en) * 1998-04-07 2000-05-23 Lsi Logic Corporation Method of forming DRAM capacitor by forming separate dielectric layers in a CMOS process
TW375836B (en) * 1998-05-04 1999-12-01 United Microelectronics Corp SRAM (static random access memory) manufacturing method
US6009023A (en) * 1998-05-26 1999-12-28 Etron Technology, Inc. High performance DRAM structure employing multiple thickness gate oxide
JP3474778B2 (ja) 1998-06-30 2003-12-08 株式会社東芝 半導体装置
US6165918A (en) * 1999-05-06 2000-12-26 Integrated Device Technology, Inc. Method for forming gate oxides of different thicknesses
JP4614481B2 (ja) * 1999-08-30 2011-01-19 ルネサスエレクトロニクス株式会社 半導体集積回路装置
KR20030001827A (ko) * 2001-06-28 2003-01-08 삼성전자 주식회사 이중 게이트 산화막을 갖는 반도체 소자의 제조방법
JP2003132683A (ja) 2001-10-23 2003-05-09 Hitachi Ltd 半導体装置
JP4153856B2 (ja) * 2003-09-30 2008-09-24 株式会社東芝 不揮発性半導体記憶装置
CN102437016B (zh) * 2011-08-17 2013-10-09 上海华力微电子有限公司 一种实现两种不同绝缘层厚度电容的集成方法
US8993457B1 (en) * 2014-02-06 2015-03-31 Cypress Semiconductor Corporation Method of fabricating a charge-trapping gate stack using a CMOS process flow
JP6383041B2 (ja) * 2017-04-06 2018-08-29 ルネサスエレクトロニクス株式会社 半導体装置

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JPS5583251A (en) * 1978-12-20 1980-06-23 Fujitsu Ltd Method of fabricating semiconductor device
JPH02237153A (ja) * 1989-03-10 1990-09-19 Fujitsu Ltd 揮発性半導体記憶装置
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
JP2776599B2 (ja) * 1990-01-25 1998-07-16 日本電気株式会社 Ｍｏｓ型ｄｒａｍ装置
US5057449A (en) * 1990-03-26 1991-10-15 Micron Technology, Inc. Process for creating two thicknesses of gate oxide within a dynamic random access memory

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Publication number Publication date
US5293336A (en) 1994-03-08
JPH04165670A (ja) 1992-06-11

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