KR910020733A - 스태틱형 메모리 - Google Patents

스태틱형 메모리 Download PDF

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Publication number
KR910020733A
KR910020733A KR1019910006556A KR910006556A KR910020733A KR 910020733 A KR910020733 A KR 910020733A KR 1019910006556 A KR1019910006556 A KR 1019910006556A KR 910006556 A KR910006556 A KR 910006556A KR 910020733 A KR910020733 A KR 910020733A
Authority
KR
South Korea
Prior art keywords
partial
bit line
time
partial circuit
select signal
Prior art date
Application number
KR1019910006556A
Other languages
English (en)
Other versions
KR950006426B1 (ko
Inventor
마사타카 마추이
Original Assignee
아오이 죠이치
가부시기가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시기가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910020733A publication Critical patent/KR910020733A/ko
Application granted granted Critical
Publication of KR950006426B1 publication Critical patent/KR950006426B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

내용 없음

Description

스태틱형 메모리
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예의 구성도, 제2도는 동 구성의 작용을 나타낸 타임 차트, 제3도 및 제4도는 각기 동 구성의 요부 상세도.

Claims (2)

  1. 워드선(WL1, WL2, …)에 의해 선택 제어되고, 기억한 2치 데이터를 비트선 쌍에 출력하는 스태틱형 메모리 셀(1,2,3,4,…)이 격자 형상으로 배열된 메모리 셀 어레이와, 이 셀 어레이의 입력 어드레스에 해당하는 메모리 셀에 접속한 워드선과 비트선 쌍을 선택 제어하고, 기록시의 워드선, 비트선 쌍의 선택 시간을 독출시의 선택시간보다도 늦게하는 지연 수단(31,32)을 갖는 어드레스 디코더 회로(5,6)를 구비하는 것을 특징으로 하는 스태틱형 메모리.
  2. 제1항에 있어서, 상기 지연 수단으로서, 기록 선택 신호에 의해 차단되는 제1의 부분 회로와, 기록 선택 신호에 의해 선택되는 기지연 회로를 갖는 제2의 부분 회로와, 이들 2종류의 부분 회로의 출력신호를 융합하는 수단을 갖는 부분디코드 회로를 포함하는 어드레스 디코드 부를 구비한 것을 특징으로 하는 스태틱형 메모리.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910006556A 1990-05-01 1991-04-24 스태틱형 메모리 KR950006426B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP02-115481 1990-05-01
JP2115481A JP2531829B2 (ja) 1990-05-01 1990-05-01 スタティック型メモリ

Publications (2)

Publication Number Publication Date
KR910020733A true KR910020733A (ko) 1991-12-20
KR950006426B1 KR950006426B1 (ko) 1995-06-15

Family

ID=14663590

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910006556A KR950006426B1 (ko) 1990-05-01 1991-04-24 스태틱형 메모리

Country Status (3)

Country Link
US (1) US5357479A (ko)
JP (1) JP2531829B2 (ko)
KR (1) KR950006426B1 (ko)

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JP3129880B2 (ja) * 1993-06-18 2001-01-31 株式会社東芝 半導体記憶装置
JP2739809B2 (ja) * 1993-07-30 1998-04-15 日本電気株式会社 半導体集積回路
US5530677A (en) * 1994-08-31 1996-06-25 International Business Machines Corporation Semiconductor memory system having a write control circuit responsive to a system clock and/or a test clock for enabling and disabling a read/write latch
US5493241A (en) * 1994-11-16 1996-02-20 Cypress Semiconductor, Inc. Memory having a decoder with improved address hold time
TW358907B (en) * 1994-11-22 1999-05-21 Monolithic System Tech Inc A computer system and a method of using a DRAM array as a next level cache memory
KR0164797B1 (ko) * 1995-03-31 1999-02-01 김광호 라이트 리커버리 제어회로 및 그 제어방법
JP3380828B2 (ja) * 1995-04-18 2003-02-24 松下電器産業株式会社 半導体メモリ装置
US6128700A (en) 1995-05-17 2000-10-03 Monolithic System Technology, Inc. System utilizing a DRAM array as a next level cache memory and method for operating same
KR100209364B1 (ko) * 1995-10-27 1999-07-15 김영환 메모리장치
KR0157289B1 (ko) * 1995-11-13 1998-12-01 김광호 컬럼 선택 신호 제어회로
US5864509A (en) * 1997-02-21 1999-01-26 Cypress Semiconductor Corp. Method and apparatus for reducing continuous write cycle current in memory device
KR100271806B1 (ko) * 1998-07-18 2000-11-15 김영환 반도체 메모리의 라이트 리커버리 시간 제어회로 및 제어방법
DE10053425C2 (de) * 2000-10-27 2003-02-13 Infineon Technologies Ag Integrierter Speicher mit Zeilenzugriffsteuerung zur Aktivierung und Deaktivierung von Zeilenleitungen
US6597623B2 (en) * 2001-06-28 2003-07-22 Intel Corporation Low power architecture for register files
KR100562504B1 (ko) * 2003-08-29 2006-03-21 삼성전자주식회사 신호의 위상차를 줄이는 반도체 메모리 장치
KR100631929B1 (ko) * 2005-02-15 2006-10-04 삼성전자주식회사 신호 딜레이 조절부를 갖는 반도체 메모리 장치
US7821866B1 (en) 2007-11-14 2010-10-26 Cypress Semiconductor Corporation Low impedance column multiplexer circuit and method
US8375172B2 (en) 2010-04-16 2013-02-12 International Business Machines Corporation Preventing fast read before write in static random access memory arrays

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JPS60690A (ja) * 1983-06-15 1985-01-05 Hitachi Ltd 書込み信号発生回路
JPS60182595A (ja) * 1984-03-01 1985-09-18 Toshiba Corp ランダムアクセスメモリ
DE3543911A1 (de) * 1984-12-14 1986-06-26 Mitsubishi Denki K.K., Tokio/Tokyo Digitale verzoegerungseinheit
US4768168A (en) * 1985-03-18 1988-08-30 Nec Corporation Memory circuit having an improved writing scheme
US4689771A (en) * 1986-03-03 1987-08-25 Motorola, Inc. Memory with improved write mode to read mode transition
JPS6342090A (ja) * 1986-08-07 1988-02-23 Fujitsu Ltd ユニバーサルジョイント
JPH01105388A (ja) * 1987-10-19 1989-04-21 Hitachi Ltd ワードライン制御回路
JP2559779B2 (ja) * 1987-12-28 1996-12-04 富士通株式会社 スタティックｒａｍ装置
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JPH07118196B2 (ja) * 1988-12-28 1995-12-18 株式会社東芝 スタティック型半導体メモリ
KR930006622B1 (ko) * 1990-09-04 1993-07-21 삼성전자 주식회사 반도체 메모리장치

Also Published As

Publication number Publication date
JP2531829B2 (ja) 1996-09-04
US5357479A (en) 1994-10-18
JPH0413294A (ja) 1992-01-17
KR950006426B1 (ko) 1995-06-15

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