KR910019119A - 반도체 웨이퍼상에 규화 티타늄을 형성시키는 단일 어닐링 방법 - Google Patents

반도체 웨이퍼상에 규화 티타늄을 형성시키는 단일 어닐링 방법 Download PDF

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KR910019119A
KR910019119A KR1019910006057A KR910006057A KR910019119A KR 910019119 A KR910019119 A KR 910019119A KR 1019910006057 A KR1019910006057 A KR 1019910006057A KR 910006057 A KR910006057 A KR 910006057A KR 910019119 A KR910019119 A KR 910019119A
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temperature
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눌만 자임
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제임스 조셉 드롱
어플라이드 머티어리얼스, 인코포레이티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3211—Nitridation of silicon-containing layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/976—Temporary protective layer

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Abstract

내용 없음

Description

반도체 웨이퍼상에 규화 티타늄을 형성시키는 단일 어닐링 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3 내지 제6도는 본 발명의 방법을 이용하여 실리콘 웨이퍼상에 형성된 규화티타늄층의 형성을 연속적으로 도시한 부분 수직 단면도.

Claims (10)

  1. 실리콘 반도체 웨이퍼상에 전도성 규화티타늄층을 형성시키는 방법이 있어서, a) 사실상 산소함유가스가 없는 진공 증착 챔버내에서 웨이퍼위에 티타늄층을 형성시키는 단계; b) 새로이 형성된 티타늄층을 산소함유가스에 노출시키지 않으면서 티타늄 피복된 웨이퍼를 밀폐된 어닐링 챔버로 이동시키는 단계; 및 c) 단일 어닐링 단계로 상기 밀폐된 어닐링 챔버내에서 질소함유 분위기에서 사실상 산소함유가스가 없이 티타늄 피복된 실리콘 반도체 웨이퍼를 어닐링 시켜 웨이퍼상에 안정된 규화 티타늄상을 형성시키고 웨이퍼상 산화 실리콘 표면위 및 규화 티타늄 위에 질화 티타늄층을 형성시키는 단계로 구성됨을 특징으로 하는 방법.
  2. 제1항에 있어서, 상기 어닐링 단계가 약 5℃/초 내지 150℃/초의 범위내 비율로 웨이퍼의 온도를 상승시킴으로써 약20내지 60초동안 약 500℃ 내지 695℃범위의 제1온도로 상기 웨이퍼를 처음으로 가열하여 상기 규화티타늄과 질화 티타늄을 형성시키는 단계를 더 포함함을 특징으로 하는 방법.
  3. 제2항에 있어서, 상기 어닐링 단계가 약20내지 60초 범위의 부가적 시간동안 약 800 내지 900℃의 제2온도에서 웨이퍼를 더 어닐링하여 규화 티타늄을 안정된 상으로 변화시키는 단계를 더 포함함을 특징으로 하는 방법.
  4. 제3항에 있어서, 상기 어닐링 단계후에 질화 티타늄을 웨이퍼로부터 제거시키기 위해 웨이퍼를 에칭시키는 단계를 더 포함함을 특징으로 하는 방법.
  5. 제1항에 있어서, 상기 어닐링 단계가 약 5℃/초 내지 150℃/초의 범위내 비율로 상기 웨이퍼의 온도를 상승시킴으로써 약 20내지 60초동안 약 500내지 695℃의 제1온도로 웨이퍼를 어닐링시키는 단계와, 약 20내지 60초의 부가적 시간동안 약 800 내지 900℃의 제2온도로 웨이퍼로 더 어닐링 하는 단계로 구성됨을 특징으로 하는 방법.
  6. 제5항에 있어서, 상기 어닐링 온도가 약 5℃/초 내지 150℃/초의 비율로 상기 웨이퍼의 온도를 상승시킴으로써 제1온도범위내에서 제2온도범위로 상승됨을 특징으로 하는 방법.
  7. 제5항에 있어서 상기 고온의 제2온도에서의 웨이퍼의 후어닐링이 산화 실리콘을 중첩하는 반응하지 않은 티타늄과 산화실리콘 사이에 반응을 일으키지 않을, 질화 티타늄을 형성하기 위해 제1온도에서 상기 어닐링중 웨이퍼상 산화 실리콘(SiO2)영역을 중첩하는 모든 티타늄과 질소의 반응을 더 포함함을 특징으로 하는 방법.
  8. 제1항에 있어서, 상기 어닐링 단계가 약 5℃/초 내지 150℃/초의 비율로 상기 웨이퍼의 온도를 상승시킴으로써 약 20내지 60초동안 약 600내지 675℃의 제1온도로 웨이퍼를 어닐링시키는 단계와, 약 5℃/초 내지 150℃/초의 비율로 웨이퍼의 온도를 더 상승시킴으로써 약 20내지 60초의 부가적 시간동안 약 800내지 900℃의 제2온도로 웨이퍼를 더 어닐링시키는 단계를 더 포함함을 특징으로 하는 방법.
  9. 제6항에 있어서, a) 상기 티타늄 증착단계전에 산화물 및 다른 재료를 웨이퍼의 실리콘 표면으로부터 제거하기 위해 세척 챔버내에 고주파 플라즈마를 유지시키면서 하나이상의 반응가스를 갖는 가스혼합물을 사용하여 웨이퍼를 세척챔버내에서 세척시키는 단계; b) 세척 챔버 및 진공 증착 챔버에 상호 연결된 약 10-9내지 10-5의 압력으로 유지되는 밀폐된 중앙챔버를 사용하여 상기 세척된 웨이퍼를 산소 및/또는 하나 이상의 산소함유가스에 노출시키지 않으면서 상기 세척된 웨이퍼를 상기 세척 챔버로부터 상기 진공 증착 챔버로 이동시키는 단계를 더 포함함을 특징으로 하는 방법.
  10. 단일 어닐링 단계를 사용하여 실리콘 반도체 웨이퍼상에 규소화 티타늄을 형성시키는 방법에 있어서, a) 규화 티타늄이 형성되어질 하나이상의 규소 표면 영역을 갖는 규소 반도체 웨이퍼를 준비하는 단계; b) 하나 이상의 반응가스를 포함하는 가스혼합물과 고주파 플라즈마를 사용하여 밀폐된 세척 챔버내에서 상기 웨이퍼를 세척시키는 단계; c) 상기 웨이퍼를 상기 진공 증착 챔버와 세척 챔버에 상호 연결된 밀폐된 중앙 챔버를 통해 이동시킴으로써 상기 세척된 웨이퍼를 산소함유가스에 본질적으로 노출시키지 않으면서 세척된 웨이퍼를 진공증착챔버로 이동시키는 단계; d) 사실상 산소함유가스가 없는 진공증착챔버내에서 상기 세척된 웨이퍼위에 티타늄층을 형성시키는 단계; e) 상기 웨이퍼를 상기 진공증착챔버 및 밀폐된 어닐링 챔버에 상호 연결된 밀폐된 중앙챔버를 통해 이동시킴으로써 새로이 형성된 티타늄층을 산소함유가스에 본질적으로 노출시키지 않으면서 티타늄 피복된 웨이퍼를 어닐링 위치로 이동시키는 단계; 및 f) 웨이퍼위의 산화 실리콘(SiO2)표면위 및 규화 티타늄위에 질화 티타늄을 형성하기 위해 약 5℃/초 내지 150℃/초의 비율로 상기 웨이퍼의 온도를 상승시킴으로써 약 20내지 60초동안 상기 웨이퍼를 약 500 내지 695℃의 제1온도로 처음으로 가열함으로써 상기 어닐링 위치에서 산소함유 가스 없이 질소함유분위기로 티타늄 피복된 실리콘반도체 웨이퍼를 어닐링시키고, 규화 티타늄을 안정된상으로 변화시키기 위해 약 20내지 60총의 부가적 시간동안 약 800내지 900℃의 제2온도로 상기 웨이퍼를 더 어닐링시키는 단계로 이루어짐을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910006057A 1990-04-16 1991-04-16 반도체 웨이퍼상에 규화 티타늄을 형성시키는 단일 어닐링 방법 KR100239608B1 (ko)

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US07/510,340 1990-04-16
US7/510,340 1990-04-16
US07/510,340 US5043300A (en) 1990-04-16 1990-04-16 Single anneal step process for forming titanium silicide on semiconductor wafer

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