KR910019047A - 캐쉬메모리 내장반도체 기억장치 - Google Patents
캐쉬메모리 내장반도체 기억장치 Download PDFInfo
- Publication number
- KR910019047A KR910019047A KR1019910005672A KR910005672A KR910019047A KR 910019047 A KR910019047 A KR 910019047A KR 1019910005672 A KR1019910005672 A KR 1019910005672A KR 910005672 A KR910005672 A KR 910005672A KR 910019047 A KR910019047 A KR 910019047A
- Authority
- KR
- South Korea
- Prior art keywords
- open
- cache
- memory
- response
- accessed
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명의 한 실시예에 의한 캐쉬 DRAM의 구성을 표시하는 블럭도.
Claims (1)
1칩상에 형성되는 캐쉬메모리 내장반도체 기억장치이고, 다중화된 열어드레스 신호 및 행어드레스 신호를 받는 어드레스 수신수단, 상기 행어드레스 신호 및 상이 열어드레스 신호에 응답하여 엑세스되는 다이내믹형 메모리 수단, 및 상기 열어드레스 신호의 적어도 일부에 응답하여 엑세스되는 스태틱형메모리 수단을 구비하고, 캐쉬히트 및 캐쉬미스 판정시에 상기 어드레스 수신수단으로부터의 상기 열어드레스 신호의 적어도 일부에 응답하여 상기 스태틱형 메모리 수단이 엑세스되어, 캐쉬미스에는 상기 어드레스 수신수단으로부터의 상기 헹어드레스 신호 및 상기 열어드레스 신호에 응답하여 상기 다이내믹형 메모리 수단이 다시금 엑세스되는 캐쉬메모리 내장반도체 기억장치.
※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9878290A JP2862948B2 (ja) | 1990-04-13 | 1990-04-13 | 半導体記憶装置 |
JP2-98782 | 1990-04-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910019047A true KR910019047A (ko) | 1991-11-30 |
KR940008140B1 KR940008140B1 (ko) | 1994-09-03 |
Family
ID=14228939
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910005672A KR940008140B1 (ko) | 1990-04-13 | 1991-04-09 | 캐쉬메모리 내장반도체 기억장치 및 그의 데이타독출방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5509132A (ko) |
JP (1) | JP2862948B2 (ko) |
KR (1) | KR940008140B1 (ko) |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2796590B2 (ja) * | 1991-08-07 | 1998-09-10 | 三菱電機株式会社 | メモリ装置及びそれを使用したデータ処理装置 |
US5867721A (en) * | 1995-02-07 | 1999-02-02 | Intel Corporation | Selecting an integrated circuit from different integrated circuit array configurations |
US6128700A (en) | 1995-05-17 | 2000-10-03 | Monolithic System Technology, Inc. | System utilizing a DRAM array as a next level cache memory and method for operating same |
JPH0916470A (ja) * | 1995-07-03 | 1997-01-17 | Mitsubishi Electric Corp | 半導体記憶装置 |
US5761695A (en) * | 1995-09-19 | 1998-06-02 | Hitachi, Ltd. | Cache memory control method and apparatus, and method and apparatus for controlling memory capable of interleave control |
US5812418A (en) * | 1996-10-31 | 1998-09-22 | International Business Machines Corporation | Cache sub-array method and apparatus for use in microprocessor integrated circuits |
US5895487A (en) * | 1996-11-13 | 1999-04-20 | International Business Machines Corporation | Integrated processing and L2 DRAM cache |
US6167486A (en) * | 1996-11-18 | 2000-12-26 | Nec Electronics, Inc. | Parallel access virtual channel memory system with cacheable channels |
US5835932A (en) * | 1997-03-13 | 1998-11-10 | Silicon Aquarius, Inc. | Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM |
JP3092557B2 (ja) * | 1997-09-16 | 2000-09-25 | 日本電気株式会社 | 半導体記憶装置 |
JP3092558B2 (ja) | 1997-09-16 | 2000-09-25 | 日本電気株式会社 | 半導体集積回路装置 |
US6192459B1 (en) * | 1998-03-23 | 2001-02-20 | Intel Corporation | Method and apparatus for retrieving data from a data storage device |
JP3173728B2 (ja) * | 1998-12-07 | 2001-06-04 | 日本電気株式会社 | 半導体装置 |
US6708254B2 (en) | 1999-11-10 | 2004-03-16 | Nec Electronics America, Inc. | Parallel access virtual channel memory system |
US6862654B1 (en) * | 2000-08-17 | 2005-03-01 | Micron Technology, Inc. | Method and system for using dynamic random access memory as cache memory |
US6779076B1 (en) | 2000-10-05 | 2004-08-17 | Micron Technology, Inc. | Method and system for using dynamic random access memory as cache memory |
US6892279B2 (en) * | 2000-11-30 | 2005-05-10 | Mosaid Technologies Incorporated | Method and apparatus for accelerating retrieval of data from a memory system with cache by reducing latency |
US6876557B2 (en) * | 2001-06-12 | 2005-04-05 | Ibm Corporation | Unified SRAM cache system for an embedded DRAM system having a micro-cell architecture |
US7634709B2 (en) * | 2001-10-05 | 2009-12-15 | Unisys Corporation | Familial correction with non-familial double bit error detection |
JP3935149B2 (ja) * | 2004-01-16 | 2007-06-20 | 株式会社東芝 | 半導体集積回路 |
US7099221B2 (en) | 2004-05-06 | 2006-08-29 | Micron Technology, Inc. | Memory controller method and system compensating for memory cell data losses |
US20060010339A1 (en) * | 2004-06-24 | 2006-01-12 | Klein Dean A | Memory system and method having selective ECC during low power refresh |
US7340668B2 (en) * | 2004-06-25 | 2008-03-04 | Micron Technology, Inc. | Low power cost-effective ECC memory system and method |
US7116602B2 (en) * | 2004-07-15 | 2006-10-03 | Micron Technology, Inc. | Method and system for controlling refresh to avoid memory cell data losses |
US6965537B1 (en) * | 2004-08-31 | 2005-11-15 | Micron Technology, Inc. | Memory system and method using ECC to achieve low power refresh |
US7653785B2 (en) * | 2005-06-22 | 2010-01-26 | Lexmark International, Inc. | Reconfigurable cache controller utilizing multiple ASIC SRAMS |
US7894289B2 (en) * | 2006-10-11 | 2011-02-22 | Micron Technology, Inc. | Memory system and method using partial ECC to achieve low power refresh and fast access to data |
US7900120B2 (en) | 2006-10-18 | 2011-03-01 | Micron Technology, Inc. | Memory system and method using ECC with flag bit to identify modified data |
US8135933B2 (en) * | 2007-01-10 | 2012-03-13 | Mobile Semiconductor Corporation | Adaptive memory system for enhancing the performance of an external computing device |
EP2418648B1 (en) * | 2010-07-29 | 2013-03-06 | STMicroelectronics (Grenoble 2) SAS | RAM memory device selectively protectable with ECC |
US8397023B2 (en) | 2010-12-18 | 2013-03-12 | Lsi Corporation | System and method for handling IO to drives in a memory constrained environment |
KR20120094778A (ko) * | 2011-02-17 | 2012-08-27 | 삼성전자주식회사 | 캐시 레이턴시 저감을 위한 캐시 메모리 제어방법 및 캐시 메모리 시스템 |
US9110829B2 (en) * | 2012-11-30 | 2015-08-18 | Taiwan Semiconductor Manufacturing Co. Ltd. | MRAM smart bit write algorithm with error correction parity bits |
KR102143517B1 (ko) * | 2013-02-26 | 2020-08-12 | 삼성전자 주식회사 | 에러 정정회로를 포함하는 반도체 메모리 장치 및 반도체 메모리 장치의 동작방법 |
KR20200104601A (ko) | 2019-02-27 | 2020-09-04 | 에스케이하이닉스 주식회사 | 컨트롤러, 메모리 시스템 및 그것의 동작 방법 |
KR102421149B1 (ko) | 2018-01-02 | 2022-07-14 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 그것의 동작 방법 |
KR102456173B1 (ko) | 2017-10-27 | 2022-10-18 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 그것의 동작 방법 |
US11573891B2 (en) | 2019-11-25 | 2023-02-07 | SK Hynix Inc. | Memory controller for scheduling commands based on response for receiving write command, storage device including the memory controller, and operating method of the memory controller and the storage device |
KR102456176B1 (ko) | 2020-05-21 | 2022-10-19 | 에스케이하이닉스 주식회사 | 메모리 컨트롤러 및 그 동작 방법 |
KR102406449B1 (ko) | 2020-06-25 | 2022-06-08 | 에스케이하이닉스 주식회사 | 스토리지 장치 및 그 동작 방법 |
KR102495910B1 (ko) | 2020-04-13 | 2023-02-06 | 에스케이하이닉스 주식회사 | 스토리지 장치 및 그 동작 방법 |
US11755476B2 (en) | 2020-04-13 | 2023-09-12 | SK Hynix Inc. | Memory controller, storage device including the memory controller, and method of operating the memory controller and the storage device |
KR102435253B1 (ko) | 2020-06-30 | 2022-08-24 | 에스케이하이닉스 주식회사 | 메모리 컨트롤러 및 그 동작 방법 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3969706A (en) * | 1974-10-08 | 1976-07-13 | Mostek Corporation | Dynamic random access memory misfet integrated circuit |
US4050061A (en) * | 1976-05-03 | 1977-09-20 | Texas Instruments Incorporated | Partitioning of MOS random access memory array |
US4498155A (en) * | 1979-11-23 | 1985-02-05 | Texas Instruments Incorporated | Semiconductor integrated circuit memory device with both serial and random access arrays |
US4382278A (en) * | 1980-06-05 | 1983-05-03 | Texas Instruments Incorporated | Hierarchial memory system with microcommand memory and pointer register mapping virtual CPU registers in workspace cache #4 and main memory cache |
JPS5956284A (ja) * | 1982-09-24 | 1984-03-31 | Hitachi Micro Comput Eng Ltd | 半導体記憶装置 |
US4577293A (en) * | 1984-06-01 | 1986-03-18 | International Business Machines Corporation | Distributed, on-chip cache |
US4649516A (en) * | 1984-06-01 | 1987-03-10 | International Business Machines Corp. | Dynamic row buffer circuit for DRAM |
US4985829A (en) * | 1984-07-31 | 1991-01-15 | Texas Instruments Incorporated | Cache hierarchy design for use in a memory management unit |
US4725945A (en) * | 1984-09-18 | 1988-02-16 | International Business Machines Corp. | Distributed cache in dynamic rams |
JPS6238590A (ja) * | 1985-08-13 | 1987-02-19 | Fujitsu Ltd | 半導体記憶装置 |
US4803621A (en) * | 1986-07-24 | 1989-02-07 | Sun Microsystems, Inc. | Memory access system |
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US4933837A (en) * | 1986-12-01 | 1990-06-12 | Advanced Micro Devices, Inc. | Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories |
US4884270A (en) * | 1986-12-11 | 1989-11-28 | Texas Instruments Incorporated | Easily cascadable and testable cache memory |
JPH01146187A (ja) * | 1987-12-02 | 1989-06-08 | Mitsubishi Electric Corp | キヤッシュメモリ内蔵半導体記憶装置 |
US4905188A (en) * | 1988-02-22 | 1990-02-27 | International Business Machines Corporation | Functional cache memory chip architecture for improved cache access |
US4953079A (en) * | 1988-03-24 | 1990-08-28 | Gould Inc. | Cache memory address modifier for dynamic alteration of cache block fetch sequence |
US5210843A (en) * | 1988-03-25 | 1993-05-11 | Northern Telecom Limited | Pseudo set-associative memory caching arrangement |
US4888773A (en) * | 1988-06-15 | 1989-12-19 | International Business Machines Corporation | Smart memory card architecture and interface |
JP2865170B2 (ja) * | 1988-07-06 | 1999-03-08 | 三菱電機株式会社 | 電子回路装置 |
US5148536A (en) * | 1988-07-25 | 1992-09-15 | Digital Equipment Corporation | Pipeline having an integral cache which processes cache misses and loads data in parallel |
US4912630A (en) * | 1988-07-29 | 1990-03-27 | Ncr Corporation | Cache address comparator with sram having burst addressing control |
US5163142A (en) * | 1988-10-28 | 1992-11-10 | Hewlett-Packard Company | Efficient cache write technique through deferred tag modification |
KR910009555B1 (ko) * | 1989-01-09 | 1991-11-21 | 조경연 | 싱글 포트 듀얼 ram(spdram) |
-
1990
- 1990-04-13 JP JP9878290A patent/JP2862948B2/ja not_active Expired - Fee Related
-
1991
- 1991-04-09 KR KR1019910005672A patent/KR940008140B1/ko not_active IP Right Cessation
-
1994
- 1994-08-01 US US08/283,487 patent/US5509132A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2862948B2 (ja) | 1999-03-03 |
JPH03296992A (ja) | 1991-12-27 |
US5509132A (en) | 1996-04-16 |
KR940008140B1 (ko) | 1994-09-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR910019047A (ko) | 캐쉬메모리 내장반도체 기억장치 | |
KR900002306A (ko) | 리프레쉬 제어회로 | |
KR890017604A (ko) | 마이크로 컴퓨터 시스템 | |
KR920010638A (ko) | 반도체 기억장치 | |
DE68919570D1 (de) | Dynamische Speicheranordnung mit wahlfreiem Zugriff vom Metall-Isolator-Halbleiter-Typ. | |
KR870008314A (ko) | 반도체 기억장치 | |
KR900006860A (ko) | 메모리 시스템 | |
EP0452510A4 (en) | Semiconductor memory device | |
KR870010549A (ko) | 반도체 기억장치 | |
KR910008730A (ko) | 반도체 기억장치 | |
KR970029834A (ko) | 어드레스 신호 변화에 대한 안정한 응답특성을 갖는 어드레스 천이 검출회로를 구비한 반도체 기억장치 | |
KR960024986A (ko) | 정보 처리 장치 | |
KR890004333A (ko) | 반도체 메모리 장치 | |
KR940022567A (ko) | 반도체 집적회로 | |
KR920003314A (ko) | 반도체 메모리장치 | |
KR910006987A (ko) | 반도체기억장치 | |
KR920001522A (ko) | 다중 포트 메모리 | |
KR920006970A (ko) | 반도체 메모리를 위한 시리얼 선택회로 | |
KR920022297A (ko) | 다이너믹 랜덤 액세스 메모리 장치 | |
KR950019006A (ko) | 옵션 처리를 이용한 리페어 효율 증가 회로 | |
KR970705085A (ko) | 캐시의 문맥이 무가치한 경우에 캐시가 판독되는 것을 방지하는 파이프라인형 마이크로프로세서(A Pipelined Microprocessor that Prevents the Cache From Being Read When the Contents of the Cache Are Invalid) | |
KR910010340A (ko) | 확장 어드레싱 회로 및 접합기 카드 | |
KR900015155A (ko) | 다이나믹형 반도체 기억 장치 | |
KR880008331A (ko) | 다이나믹 램 | |
KR910012928A (ko) | 컴퓨터의 메모리 확장 시스템 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20060824 Year of fee payment: 13 |
|
LAPS | Lapse due to unpaid annual fee |