US5835932A - Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM - Google Patents
Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM Download PDFInfo
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- US5835932A US5835932A US08/816,663 US81666397A US5835932A US 5835932 A US5835932 A US 5835932A US 81666397 A US81666397 A US 81666397A US 5835932 A US5835932 A US 5835932A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
Definitions
- the present invention relates in general to electronic memories and in particular to a dynamic random access memory (DRAM) with integral static random access memory (SRAM, and systems and methods using the same.
- DRAM dynamic random access memory
- SRAM integral static random access memory
- DRAMs dynamic random access memories
- the typical general purpose DRAM has a single data port for writing and reading data to and from addressed storage locations ("dual ported" DRAMs are available which provide two data ports, typically one random and one serial port, however, these devices are normally limited to special memory applications).
- Second, data writes and reads are only made on a location by location basis, with each location typically being one bit, one byte or one word wide.
- PCs personal computers
- CPU central processing unit
- All other subsystems, such as the display controller, disk drive controller, and audio controller then operate as slaves to the CPU.
- This master/slave organization is normally used no matter whether the CPU is a complex instruction set computer (CISC), reduced instruction set computer (RISC), Silicon Graphics MIPS device or Digital Equipment ALPHA device.
- CISC complex instruction set computer
- RISC reduced instruction set computer
- Silicon Graphics MIPS device Silicon Graphics MIPS device
- Digital Equipment ALPHA device Digital Equipment ALPHA
- Multiprocessing architectures are not yet cost effective for application in the PC environment.
- memory contention and bus contention are still significant concerns in any multiprocessing system, let alone in a multiprocessing PC environment.
- a memory which includes a plurality of banks each including first and second arrays of memory cells, first accessing circuitry for selectively accessing cells in the first array and second accessing circuitry for selectively accessing cells in the second array.
- Each bank further includes storage circuitry for storing address bits and circuitry for comparing received address bits with stored address bits in the storage circuitry.
- the first accessing circuitry accesses cells in the first array in response to the stored address bits when the stored address bits and the received address bits match.
- the second accessing circuitry accesses cells in the second array when the stored address bits and the received address bits differ.
- the global access control circuitry enables comparison of the stored address bits and the received address bits in a selected one of the plurality of banks.
- a memory subsystem including a plurality of memory banks each comprising an array of rows and columns of dynamic random access memory cells, a row decoder for selecting one of the dynamic random access memory cells for access, an array of static random access memory cells coupled to the array of dynamic random access memory cells, and a latch for storing a selected number of row address bits.
- Each bank further includes comparator circuitry for selectively comparing received row address bits and row address bits stored in the latch of the bank, the comparator circuitry initiating an access to selected cells in the static random access array when the received bits and the stored bits match and initiating an access to selected cells in the dynamic random access array when the received row address bits and the stored row address bits differ.
- the memory subsystem further includes a global row assignor for enabling the comparator circuitry of a selected one of the banks in response to selected bits of a received row address.
- an address is received having first and second sets of bits.
- a first of a plurality of banks is selected in response to the first set of bits and the second set of bits are compared with bits previously stored in first one of the banks.
- a selected one of an SRAM array and a DRAM array in the first of the banks is accessed.
- the SRAM array is accessed and if the second set of bits stored in the selected banks differ, the DRAM array is accessed.
- a first address comprising a first plurality of address bits is received.
- First data is written to a location in a first one of the banks addressed by the first plurality of bits.
- the first plurality of bits are also stored in the first bank.
- the first plurality of address bits are also modified to generate a second plurality of address bits.
- Second data is then written to a location in a second one of the banks addressed by the second plurality of address bits.
- the second plurality of address bits are stored in the second bank.
- a second address, including a third plurality of address bits, is received.
- the third plurality of address bits are compared with the first and second plurality of bits and the first bank is accessed if the first plurality of bits matches the third plurality of bits and the second bank is accessed if the second plurality of bits matches the third plurality of bits.
- the principles of the present invention allow for the construction of high speed memory devices.
- the use of SRAM allows data to be clocked out rapidly and with additional drive.
- FIGS. 1A and 1B are block diagrams respectively depicting two basic system architectures 100A and 100B typical of those found in personal computers (PCs);
- FIG. 2A depicts a multiprocessing system in which each processor operates in conjunction with private system memory
- FIG. 2B depicts a multiprocessing system in which each processor operates in conjunction with a public system memory
- FIG. 2C depicts a multiprocessing system in which each processor operates in conjunction with both private memory and public system memory;
- FIG. 3A is a diagram illustrating a "loosely coupled" multiprocessing architecture in which each processing node maintains a dedicated copy of the operating system and a dedicated copy of the applications program;
- FIG. 3B depicts a "tightly coupled" multiprocessing system in which all processing nodes share a single copy of the operating system and a single copy of the applications program;
- FIG. 3C is a diagram of a "snugly coupled" multiprocessing system in which each processing node maintains a dedicated copy of the operating system and all nodes share a single copy of the applications program;
- FIG. 4 is a functional block diagram of a dynamic random access memory device according to one embodiment of the principles of the present invention.
- FIG. 5 is a more detailed diagram emphasizing the data and address routing circuitry of the memory shown in FIG. 4.
- FIGS. 1-5 of the drawings in which like numbers designate like parts.
- FIGS. 1A and 1B are block diagrams respectively depicting two basic system architectures 100A and 100B typical of those found in personal computers (PCs). While numerous variations on these basic architectures exist, FIGS. 1A and 1B are suitable for describing the basic structure and operation of most PCs.
- Both systems 100A and 100B include a single central processing unit 101, CPU local data bus 102, CPU local address bus 103, external (L2) cache 104, core logic/memory controller 105, and system memory 106.
- the peripherals 108 are coupled directly to core logic/memory controller 105 via a bus 107.
- Bus 107 in this case is preferably a peripheral controller interface (PCI) bus, although alternatively it could be an ISA, general, or special purpose bus, as known in the art.
- PCI peripheral controller interface
- core logic/memory controller 105 is again coupled to bus 107.
- a PCI bus bridge then interfaces bus 107 with a PCI bus 110, to which the peripherals 111 couple.
- An additional bus 112 which may be a ISA, PCI, VESA, IDE, general, or special purpose bus, is provided for access to peripherals 111 from an external device or system (not shown).
- CPU 101 In single CPU systems 10A and 100B, CPU 101 is the "master" which, in combination with the operating system and applications software, controls the overall operation of system 100. Among other things, CPU 101 performs various data processing functions including numerical and word processing, generates graphics data, and performs overall system management.
- CPU 101 may be for example a complex instruction set computer (CISC), such as an Intel Pentium class microprocessor, a reduced instruction set computer (RISC), such as a Apple PowerPC microprocessor, or a very long instruction word (VLIW) machine.
- CISC complex instruction set computer
- RISC reduced instruction set computer
- VLIW very long instruction word
- CPU 101 communicates with the remainder of system 100 via CPU local address and data buses 102 and 103, each of which may be for example a special bus, or a general bus, as known in the art.
- Core logic/memory controller 105 under the direction of CPU 101, controls the exchange of data, addresses, control signals and instructions between CPU 101, system memory 105, and peripherals 108/111 via bus 107 and/or PCI bus bridge 109. Although the core logic/memory controller allows tasks to be shifted from the CPU, thereby allowing the CPU to attend to other CPU-intensive tasks, the CPU can always override core logic/memory controller 105 to initiate execution of a higher priority task.
- the memory controller can be either a separate device or incorporated into the same chip set as the core logic.
- the memory controller is generally responsible for generating the memory clocks and control signals such as /RAS, /CAS, R/W and bank select, and monitors and controls cell refresh.
- the memory controller may also have some address generation capability for accessing sequences of pages.
- the core logic is typically comprised of a chip-set, with one or more chips typically being “address and system controller intensive” and one or more chips typically being “data intensive.”
- the address intensive chip(s) interfaces CPU 101 with address bus 103; maintains cache memory, including the cache tags, set associative cache tags and other data necessary to insure cache coherency; performs cache "bus snooping"; generates the control signals required for DRAMs in the system memory or cache; and controls general management transactions.
- the data intensive chip(s) generally: interfaces CPU 101 with the data bus 102; issues cycle completion responses; may abort operations if their cycles are incomplete; and arbitrates for the data path of bus 102.
- L2 cache 104 may be for example a 256 KByte fast SRAM device(s).
- the CPU also maintains up to 16 kilobytes of on-chip (L1) cache.
- PCI bus bridges such as PCI bus bridge 109, are also well known to those skilled in the art.
- the CPU is the bus master for the entire system and hence devices such as PCI bus bridge are slave devices which operate under command of the CPU.
- Peripherals 107/111 may include a display controller and associated frame buffer, floppy drive controller, disk driver controller, and/or modem, to name only a few options.
- FIGS. 2A, 2B and 2C respectively depict exemplary multiprocessor architectures 200A, 200B and 200C for discussion purposes.
- Multiprocessing system 200A is based upon n number of CPUs 201.
- Each CPU 201 is associated with a dedicated cache 202 and dedicated (private) system memory 203.
- Common bus 204 allows a given CPU to exchange information with peripherals, including mass storage subsystems 204, such as disk drives, tape drives and cartridge units, and Input/Output subsystems 206, such as printers, displays and keyboards.
- NORMA no read/write memory access
- System 200B also primarily includes n number of CPUs 201, each with an associated cache 202, and coupled to the peripheral devices through a common bus 204.
- system memory 207 is also coupled to bus 204 and is shared by all the CPUs 201.
- a second bus 208 is provided as a second path for accessing system memory 207.
- the memory architecture of system 200B is typically designated as a unified memory access (UMA) architecture. Under the UMA paradigm, all processors have equal access to system memory and all processors have local cache.
- UMA unified memory access
- the unified memory access architecture typically provides the fastest possible interaction between processors and is the common architecture used in PCs, work stations, and other desktop computing devices. UMA based systems are often referred to as "symmetric-multiprocessing" systems.
- System 200C is a system in which both private and system memory are provided. Specifically, in addition to dedicated cache 202, each CPU 201 is also associated with private memory 209. Each CPU is further connected by bus 204 to a shared system memory 210.
- the memory architecture of system 200C falls under the non-uniform memory access (NUMA) paradigm.
- NUMA non-uniform memory access
- each processor has a private memory and additionally shares system memory with the other processors in the system.
- One difficulty in a NUMA based system is the fact that the access times for the private and system memories may be different creating timing problems.
- FIGS. 2A, 2B and 2C there are a number of ways to implement the hardware architectures shown in FIGS. 2A, 2B and 2C in a complete hardware/software system. Three such systems are shown in FIGS. 3A-3C, respectively.
- FIG. 3A is a diagram illustrating a "loosely coupled" multiprocessing architecture.
- each processing node 300 maintains a dedicated copy of both the operating system and the application programs.
- Loosely coupled architectures such as that shown in FIG. 3A, are used often in embedded systems and in real-time systems in which tasks must be partitioned to different processing nodes for synchronization purposes.
- Embedded systems include those in which the CPU is fabricated on the same chip as logic, memory, a signal processor, or the like.
- High speed interconnects are used to share data and pass messages between processing nodes 300. While loosely coupled systems are more fault and error tolerant, their software programming is most often highly complex.
- FIG. 3B depicts a "tightly coupled" system.
- a single copy of the operating system and a single copy of the application program are shared and executed by a single set of processors.
- writing software programs for a tightly coupled system is normally simpler than for writing programs to a loosely coupled system.
- tightly coupled systems based only on single copies of the application programs and operating system, are less tolerant to errors and failures than the loosely coupled systems.
- FIG. 3C is a diagram of a "snugly coupled" system in which each processing node 300 maintains a dedicated copy of the operating system and all nodes share a single copy of the applications program.
- the snugly coupled variation is a hybrid which provides the tolerance to failure/errors found in loosely coupled systems while still providing the simpler program found in tightly coupled systems.
- CISC CPU may be "latency” dominated while a digital signal processor (DSP) based system may be “dataflow” dominated.
- DSP digital signal processor
- pipelined processing algorithms typically are dataflow intensive, since the processors perform operations on streams of data received from other processors in the system and then pass the results on to other processors.
- contention problems can be solved by "memory locking."
- memory locking is a memory management task which may be performed by the memory management unit (MMU) on-board the CPUs themselves or by a stand-alone device or subsystem. In any event, memory locking reduces the efficiency which multiprocessing was intended to increase, since during a contention situation, at least one processor must wait to access data.
- MMU memory management unit
- Symmetric multiprocessing operating systems are preferred, since this type of operating system is capable of seamlessly passing application programs to the CPUs as they become available.
- the selection of between tightly, loosely and snugly coupled software architecture requires substantial trade-offs, and in particular trade offs between ease of programming and fault/error tolerance.
- bus contention problems may also arise. Specifically, when a shared bus is employed, only one processor is normally granted access to the bus to perform a given bus task, while the remainder of the processors coupled to that bus must wait until their priority has been reached.
- One technique for minimizing bus contention problems is to provide a dedicated cache for each CPU, as shown in FIGS. 3A-3C, so that a given CPU need only access the bus at times when required data are not found in the dedicated cache.
- cache coherency is a major concern in the design of a multiprocessing system. In other words, when a given processor modifies a location in memory, some technique must be provided for insuring that the data is modified in the cache memory of each of the other processors using the same data.
- FIG. 4 is a functional block diagram of a dynamic random access memory device 400 according to one embodiment of the principles of the present invention.
- Memory 400 includes N number of memory banks or units 401, with four such banks 401a, 401b, 401c, and 401d being shown in FIG. 4 for discussion; the actual number of banks will vary from application to application, although N is preferably an even number two or greater.
- Banks 401 communicate with external circuitry through control and configuration circuitry 407, discussed further below.
- memory subsystem 400 may be used to construct system memory 102, although many other applications in the single CPU personal computer environment are possible, such as in the display frame buffer.
- memory subsystem 400 can be used to construct either the system memories or the local (private) memories.
- subsystem 400 is a monolithic integrated circuit device.
- Each bank 401 includes an array 402 of dynamic random access memory (DRAM) cells arranged in N number rows and M number columns. As is known to those skilled in the art, each array 402 may be partitioned into multiple subarrays, with the columns organized using either an open-bitline or folded-bitline approach.
- Each bank 401 further includes a traditional DRAM row decoder 404 coupled to the array wordlines, and traditional DRAM sense amplifiers/column decoder circuitry 405 coupled to the array bitlines.
- the row and column decoders are preferably organized in hierarchical fashion in which a main decoder and one or more levels of subdecoders/drivers are used.
- each row decoder 404 in response to a row address, selects one of N rows for access during an active cycle when the row address strobe /RAS is in a logic low state.
- Column decoder selects P number of pages (locations) of C number of columns (bits) from the M total number of columns in response to P number of column addresses for access during an active cycle.
- Global row assignor 406 performs a "coarse granularity decoding" using L number of least significant row address bits from each received row address. Specifically, all banks 401 are active during each /RAS cycle, and global row assignor using the L least significant row address bits to select. Row decoders 404 consequently decode the Y-1 number of remaining most significant address bits to simultaneously select one row per /RAS cycle in each DRAM array during a DRAM access.
- Control circuitry 407 receives conventional DRAM control signals and clocks from an external source, such as processor 101 or core logic 105 in system 100 or CPUs 201 in multiprocessing systems 200A-200C. These signals include a synchronous clock (SCLK), a row address strobe (/RAS), a column address strobe (/CAS), read/write select (R/W) and output enable (/OE), along with data (DQ) and addresses (A dd ). Control circuitry 407 also inputs a configuration bit (CONFIG), discussed below. In the preferred embodiment, the address input port is multiplexed in a conventional manner wherein row addresses and column addresses are received sequentially at the same pins and latched in with /RAS and /CAS respectively.
- CONFIG configuration bit
- each bank 401 further includes static random access memory (SRAM)/SRAM column decoder circuitry 408.
- SRAM circuitry 408 will be discussed in further detail in conjunction with FIG. 6, but can generally be described at this point as follows. First, a linear array of M number of SRAM cells is included for storing a row of data transferred from the corresponding DRAM array 402. Second, SRAM column decoder circuitry is included for page access (reads or writes) of C-bit wide pages of data to the row of data in SRAM array in response to one or more column addresses.
- Data latches 409 interface the DRAM sense amplifiers/column decoders 405 and the SRAM column decoders 408 with a data bus 410.
- Column addresses are transferred via a column address bus 411 and row addresses by a row address bus 412.
- Address latches and last row read (LRR) compare circuitry 413 includes latches for storing the current row and column addresses received at the address port A dd 0-A dd Y. Also included as part of circuitry 413 are latches for storing the high order (MSB) row address bits of the last row read (LRR) and comparison circuitry for comparing the stored LRR bits to the high order bits (MSB) of the current row address.
- MSB high order row address bits of the last row read
- MSB high order bits
- the least significant row address bits are processed by global assignor 406 and the most significant row address bits are used internal to the banks 401 to select individual rows of cells, other arrangements will just as easily apply. For example, a given number of most significant row address bits could be used by global row assignor 406 and the remaining least significant bits used for individual row select. Further, either big- or little-endian data structures can be used.
- the number of address bits presented to the SRAM cache of a given bank 408 is identical to the number of MSB address bits presented to DRAM row decoder 404.
- FIG. 5 is a more detailed diagram emphasizing the data and address routing circuitry of a selected bank 401. Addresses are received in a multiplexed fashion at the address port Add0-AddY. The row address bits are latched on the falling edge of /RAS (which follows the SCLK) into row address latch 501. The most significant bits are presented to the fine granularity row decoders 404 and the least significant bits to the global row assignor 406. The most significant row address bits from the previous (last) /RAS cycle are transferred to last row read address latch 502. Comparison circuitry 503 compares the most significant row address bits latched into row address latch 501 and the last read row address held in latch 502. During each /CAS cycle, one or more column addresses are received at address port Add0-AddY and latched into column address latch 504 with each falling edge of /CAS.
- /RAS which follows the SCLK
- SRAM registers 506 store data associated with the address bits stored last read address latch 502 (i.e., assuming that row addresses and data are considered together as a data structure, the row address MSBs comprise the row field and the data bits, the data field).
- a second column decoder 507 is provided to access locations in SRAM registers 506.
- a row address is first received at address pins Add0-AddY.
- the least significant row address bits (in the four bank embodiment, the two least significant bits) are passed to global row assignor 406 and the remaining most significant bits are latched into row address latch 501 of each bank 401.
- the most significant bits stored in each row address latch 501 from the previous /RAS cycle are transferred into the corresponding LRR address latch 502.
- the bit CONFIG at the input to memory 400 is set to a logic low.
- Global row assignor 406 determines from the current least significant row address bits the bank 401 which corresponds to the address space of the received address.
- the comparator 503 of the corresponding bank 401 is enabled such that during the period between the falling edge of /RAS and the first high to low transition of /CAS, that comparator 503 compares the current address most significant bits in the corresponding row address latch 501 and bits stored in LRR address latch 502. If a match occurs for the given bank, the SRAM column address decoders 507 are selected and set-up to access the complete SRAM cell array 506 of that bank.
- Column addresses received at the address port Add0-AddY are latched into column address latches 504 of each bank and each SRAM column decoder 507 accordingly allows access to a C-bit word per each of P number of column addresses latched-in with /CAS.
- the accesses are implemented through a C-bit wide data bus 410; if for example, each bank is organized as a by 16 device, data bus 410 is 16-bits wide and so on.
- the selected (enabled) bank is the only bank 401 accessed via data bus 410, the word of data in the data latches 409 of the other banks is simply not used.
- the row is selected by DRAM row decoder 404 from the corresponding DRAM array 402 and an entire row of data transferred to the associated SRAM array 506 for output when the column addresses are presented.
- the MSBs are incremented or decremented using the corresponding row address increment circuitry 508. A row of data for these banks is similarly transferred to the corresponding SRAM arrays 507.
- the received row address has LSBs 01 indicating the address space of bank 401b (Bank1) is to be accessed.
- Global row assignor 406 hence enables Bank1 to make the comparison of the row current address MSBs and the bits stored in the Bank1 LRR latch.
- the row address MSBs as received are not modified for transferring data from the bank 401b DRAM array 402 to the Bank1SRAM array.
- the row address MSBs are decremented by 01 by the corresponding row increment circuitry 508 and the row address MSBs for banks 401c (Bank2) and 401d (Bank3) are incremented by 01 and 10 respectively.
- address A+1 is decremented by one such that Bank0 receives address A0 and incremented such that Bank2 receives address A+2 and Bank3 receives address A+3.
- address A+1 is decremented by one such that Bank0 receives address A0 and incremented such that Bank2 receives address A+2 and Bank3 receives address A+3.
- the DRAM of any bank including in this case the DRAM array 402 of Bank1 can be refreshed.
- the DRAM column decoders 405 isolate the corresponding DRAM arrays 402 from the SRAM arrays 408.
- Refresh is preferably performed by incrementing the row addresses in each bank using increment and refresh circuitry 508 and latching each row of data using the DRAM sense amplifiers 405 in a conventional fashion.
- the /RAS cycle is complete.
- the data in the SRAM arrays 506 of the remaining banks 401 is available through the associated data latches 409, and could be used, but typically is reserved for future /RAS cycles.
- the current row address MSBs for the selected banks and the new row address MSBs are transferred to the LRR registers during the next /RAS cycle.
- the corresponding data remain in the SRAM arrays.
- the CPU and/or operating system typically accesses data within temporally or spacially adjacent areas in memory, the probability is substantial that a match will occur.
- An address is received at address port Add0-AddY.
- global row assignor 406 determines the bank 401 assigned to the corresponding row address space. Assume again for example, the LSBs are 01, addressing bank 401b (Bank1). The received row MSBs are taken as the address to the Bank1 DRAM array 402. As was done above, the row address increment circuitry 508 for Bank0 decrements the received row MSBs to obtain a row address to the Bank0 DRAM array and increments the received MSBs by 01 and 10 to obtain row addresses to the DRAM arrays of Bank2 and Bank3 respectively. The MSB row address bits for each bank 401 is written into the bank's LRR register 502.
- the CONFIG bit at the input to memory 400 is set high.
- the MSBs of a received address are compared by all the comparators 503. If a match occurs in any one or more banks 401, the data from all the banks is taken, although the data from the non-matching banks may be discarded or left in the data latches.
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Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
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US08/816,663 US5835932A (en) | 1997-03-13 | 1997-03-13 | Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM |
US08/855,944 US5890195A (en) | 1997-03-13 | 1997-05-14 | Dram with integral sram comprising a plurality of sets of address latches each associated with one of a plurality of sram |
TW087103567A TW389903B (en) | 1997-03-13 | 1998-03-11 | DRAM with integral SRAM and systems and methods using the same |
JP53988398A JP2001525086A (en) | 1997-03-13 | 1998-03-13 | DRAM with integrated SRAM and system and use thereof |
EP98911655A EP0966741B1 (en) | 1997-03-13 | 1998-03-13 | Dram with integral sram and systems and methods using the same |
PCT/US1998/005048 WO1998040891A1 (en) | 1997-03-13 | 1998-03-13 | Dram with integral sram and systems and methods using the same |
DE69815308T DE69815308D1 (en) | 1997-03-13 | 1998-03-13 | DRAM WITH INTEGRAL SRAM AND SYSTEMS AND METHOD FOR THE USE THEREOF |
AT98911655T ATE242536T1 (en) | 1997-03-13 | 1998-03-13 | DRAM WITH INTEGRAL SRAM AND SYSTEMS AND METHODS FOR USE THEREOF |
KR1019997008320A KR20000076226A (en) | 1997-03-13 | 1998-03-13 | Dram with integral sram and systems and methods using the same |
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Application Number | Priority Date | Filing Date | Title |
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US08/816,663 US5835932A (en) | 1997-03-13 | 1997-03-13 | Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM |
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US08/855,944 Expired - Lifetime US5890195A (en) | 1997-03-13 | 1997-05-14 | Dram with integral sram comprising a plurality of sets of address latches each associated with one of a plurality of sram |
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US08/855,944 Expired - Lifetime US5890195A (en) | 1997-03-13 | 1997-05-14 | Dram with integral sram comprising a plurality of sets of address latches each associated with one of a plurality of sram |
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AT (1) | ATE242536T1 (en) |
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TW (1) | TW389903B (en) |
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Cited By (22)
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US5890195A (en) * | 1997-03-13 | 1999-03-30 | Silicon Aquarius, Inc. | Dram with integral sram comprising a plurality of sets of address latches each associated with one of a plurality of sram |
US5903491A (en) * | 1997-06-09 | 1999-05-11 | Micron Technology, Inc. | Single deposition layer metal dynamic random access memory |
US6274928B1 (en) | 1995-08-17 | 2001-08-14 | Micron Technology, Inc. | Single deposition layer metal dynamic random access memory |
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Also Published As
Publication number | Publication date |
---|---|
US5890195A (en) | 1999-03-30 |
JP2001525086A (en) | 2001-12-04 |
EP0966741B1 (en) | 2003-06-04 |
WO1998040891A1 (en) | 1998-09-17 |
TW389903B (en) | 2000-05-11 |
KR20000076226A (en) | 2000-12-26 |
EP0966741A1 (en) | 1999-12-29 |
ATE242536T1 (en) | 2003-06-15 |
DE69815308D1 (en) | 2003-07-10 |
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